Self contained array timing

• US 4,608,669 A
• Filed: 05/18/1984
• Issued: 08/26/1986
• Est. Priority Date: 05/18/1984
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Klara, Walter S., Rasmussen, Robert A., Marcello, Victor, Kwap, Theodore W.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Miller, Guy M.
• Application Number:
  US06/611,817
• Time in Patent Office: 830 Days
• Field of Search: 365/201, 365/194, 365/233, 324/158 T, 324/73 AT, 371/21
• US Class Current: 365/201
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An on-chip apparatus for generation of timing signals for a large scale integrated (LSI) chip or semiconductor memory array is disclosed. This apparatus may be used both during the production testing of the memory and during normal functional operation. In the testing environment it allows use of much less expensive peripheral test equipment, while also providing for much greater accuracy in determination of whether or not the memory array meets its timing specification. Use during normal functional operation (subsequent to use in the test environment) provides for a guarantee of defect free operation.

Claims

1. A process for testing a read/write memory array embedded within an integrated circuit device, said integrated circuit device including, a READ/WRITE memory array, address latch circuit means having an output connected to said READ/WRITE memory array, data input latch circuit means having an output connected to said READ/WRITE memory array, data output latch circuit means having an input connected to said READ/WRITE memory array, timing control network circuit means, said timing control network circuit means having a trigger signal chip input, a READ/WRITE control chip input and first, second, third and fourth outputs, said first, second, third and fourth outputs of said timing control network circuit means being respectively connected to said address latch circuit means, said data input latch circuit means, said READ/WRITE memory array and said output latch circuit means, said process comprising the following steps:

(a) select the WRITE mode for the array by conditioning the READ/WRITE control chip input of the timing control network;

(b) place the desired memory address on address input lines of the address latch circuit means;

(c) place the desired data bits on data input lines of the data input latch circuit means; and

,

(d) provide a trigger signal from off chip to the trigger signal chip input of the timing control network

whereby the WRITE timing sequence for the memory array will be automatically generated by the timing control network and the desired data will be written into the memory array at the desired address.

2. A process for testing a read/write memory array embedded within an integrated circuit device, as recited in claim 1, wherein subsequent to step (d) of claim 1 the following steps are performed:

(e) select the READ mode for the array by conditioning the READ/WRITE control chip input of the timing control network;

(f) place said desired address on the address input lines of the address latch circuit means; and

,

(g) provide a trigger signal from off chip to the trigger signal chip input of the timing control network,

whereby the READ timing sequence for the memory array will be automatically generated by the timing control network and the output latches will capture within a predetermined time the data stored in said READ/WRITE memory array at said desired address.

3. In an integrated circuit chip, a memory array, said memory array including:

a plurality of memory elements for storing binary data, said stored binary data being arranged within said array at a plurality of addressable locations;

controllable write circuits means for writing data into said memory array at a predetermined address within said array;

controllable read circuit means for reading data stored in said memory array at a predetermined address within said array;

gated address latch circuit means coupled to said controllable write circuit means and said controllable read circuit means, said gated address circuit means providing said predetermined address to said write circuit means or said read circuit means;

gated data input latch circuit means coupled to said controllable write circuit means, said gated input latch circuit means providing data to be written into said memory array at said predetermined address provided by said address latch circuit means;

gated data output latch circuit means coupled to said controllable read circuit means, said gated output latch circuit means receiving the binary data read from the memory array as indicated by the predetermined address by said controllable read circuit means; and

said integrated circuit chip being further characterized by the inclusion of timing control network circuit means, said timing control network circuit means coupled to and controlling said controllable write circuit means and said controllable read circuit means, said timing control network circuit means also being coupled to said gated address latch circuit means, said gated data input circuit means and said gated data output circuit means, said timing control network on said integrated circuit chip including a trigger signal responsive tapped delay line and said timing control network providing all timing control signals for the operation of said memory array contained on said integrated circuit chip upon receipt of a trigger signal subsequent to the conditioning of an on chip READ/WRITE control input.

4. A process for reading data from a READ/WRITE memory array embedded within an integrated circuit device, said integrated circuit device including a READ/WRITE memory array, address latch circuit means having an output connected to said READ/WRITE memory array, data input latch circuit means having an output connected to said READ/WRITE memory array, data output latch circuit means having an input connected to READ/WRITE memory array, timing control network circuit means, said timing control network circuit means having a trigger signal chip input, a READ/WRITE control chip input and first, second, third and fourth outputs, said first, second third and fourth outputs of said timing control network circuit means being respectively connected to said address latch circuit means, said data input latch circuit means, said READ/WRITE memory array and said output latch circuit means, said process comprising the following steps:

(a) select the READ mode for the array by conditioning the READ/WRITE control chip input of the timing control network;

(b) place the desired memory address on address input lines of the address latch circuit means; and

,

(c) provide a trigger signal from off chip to the trigger signal chip input of the timing control network,

whereby a READ timing sequence for the memory array will be automatically generated by the timing control network and the output latches will capture within a predetermined time the data stored in said READ/WRITE memory array at said desired address.

5. In a READ/WRITE memory array embedded within an integrated circuit device contained on a semiconductor chip, said integrated circuit device including memory array circuit means, said memory array circuit means including, a READ/WRITE memory array, address latch circuit means having on chip inputs for receiving an address and output means connected to said memory array, data input latch circuit means having on chip inputs for receiving input data and output means connected to said memory array, data output latch circuit means having on chip inputs connected to said READ/WRITE memory array and output means for providing a data output, and a timing control network, said timing control network having a trigger signal chip input terminal, a READ/WRITE control chip input terminal and first, second, third and fourth outputs, said first, second, third and fourth outputs of said timing control network being respectively connected to said address latch circuit means, said input latch circuit means, said READ/WRITE memory array and said output latch circuit means, said timing control network upon conditioning of said READ/WRITE control and in response to a trigger signal automatically providing a "WRITE" timing sequence for a "WRITE" mode of operation of said READ/WRITE memory array or a "READ" timing sequence for a "READ" mode of operation of said read/write memory array, said timing control network comprising:

a control input terminal adapted to receive a control signal from off chip;

said trigger signal chip terminal adapted to receive a trigger signal from off chip;

said read/write control chip input terminal adapted to receive a read/write signal from off chip;

an on-chip output control terminal connected to said output latch circuit means;

an on-chip data input control terminal connected to said data input latch circuit means;

an on-chip address control terminal connected to said address latch circuit means;

an on-chip write clock control terminal connected to said read/write memory array;

n serially connected INVERTER circuits, where n is an integer, said n serially connected INVERTER circuits forming a delay circuit having an input, an output and at least first, second, third and fourth (time displaced) spaced apart taps;

a single INVERTER circuit having an input connected to said read/write input terminal of said timing control network and an output;

a first AND-INVERTER circuit having a first input connected to said trigger input terminal of said timing control network, a second input, and an output connected to said input of said delay circuit formed by said n serially connected INVERTER circuits;

a second AND-INVERTER circuit having a first input connected to said control input terminal of said timing control network, a second input connected to said output of said delay circuit formed by said n serially connected INVERTER circuits and an output connected to said second input of said first AND-INVERTER circuit;

a first OR-INVERTER circuit having a first input connected to said read/write input terminal of said timing control network, a second input connected to said output of said first AND-INVERTER circuit, a third input connected to said second tap on said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip data input control terminal of said timing control network;

a second OR-INVERTER circuit having a first input connected to said output of said first AND-INVERTER circuit, a second input connected to second tap on said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip address control terminal of said timing control network;

a third OR-INVERTER circuit having a first input connected to said read/write input terminal of said timing control network, a second input connected to said first tap on said delay circuit formed by said n serially connected INVERTER circuits, a third input connected to said third tap on said delay circuit formed by said n serially connected delay circuits and an output connected to said on-chip write clock control terminal of said timing control network; and

,

a fourth OR-INVERTER circuit having a first input connected to said output of said single INVERTER circuit, a second input connected to said fourth tap of said delay circuit formed by said n serially connected INVERTER circuits, a third input connected to said output of said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip data output control terminal of said timing control network.

6. In a READ/WRITE memory array embedded within an integrated circuit device contained on a semiconductor chip, said integrated circuit device including memory array circuit means, said memory array circuit means including, a READ/WRITE memory array, address latch circuit means having on chip inputs for receiving an address and output means connected to said memory array, data input latch circuit means having on chip inputs for receiving input data and output means connected to said memory array, data output latch circuit means having on chip inputs connected to said READ/WRITE memory array and output means for providing a data output, and a timing control network, said timing control network having a trigger signal chip input terminal, a READ/WRITE control chip input terminal and first, second, third and fourth outputs, said first, second, third and fourth outputs of said timing control network being respectively connected to said address latch circuit means, said input latch circuit means, said READ/WRITE memory array and said output latch circuit means, said timing control network upon conditioning of said READ/WRITE control and in response to a trigger signal automatically providing a "WRITE" timing sequence for a "WRITE" mode of operation of said READ/WRITE memory array or a "READ" timing sequence for a "READ" mode of operation of said read/write memory array, said timing control network comprising:

a control input terminal adapted to receive a control signal from off chip;

said trigger signal chip terminal adapted to receive a trigger signal from off chip;

said read/write control chip input terminal adapted to receive a read/write signal from off chip;

an on-chip output control terminal connected to said output latch circuit means;

an on-chip data input control terminal connected to said data input latch circuit means;

an on-chip address control terminal connected to said address latch circuit means;

an on-chip write clock control terminal connected to said read/write memory array;

n serially connected INVERTER circuits, where n is an integer, said n serially connected INVERTER circuits forming a delay circuit having an input, an output and at least first, second, third and fourth (time displaced) spaced apart taps;

a single INVERTER circuit having an input connected to said read/write input terminal of said timing control network and an output;

a first AND-INVERTER circuit having a first input connected to said trigger input terminal of said timing control network, a second input, and an output connected to said input of said delay circuit formed by said n serially connected INVERTER circuits;

a second AND-INVERTER circuit having a first input connected to said control input terminal of said timing control network, a second input connected to said output of said delay circuit formed by said n serially connected INVERTER circuits and an output connected to said second input of said first AND-INVERTER circuit;

a first OR-INVERTER circuit having a first input connected to said read/write input terminal of said timing control network, a second input connected to said output of said first AND-INVERTER circuit, a third input connected to said second tap on said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip data input control terminal of said timing control network;

a second OR-INVERTER circuit having a first input connected to said output of said first AND-INVERTER circuit, a second input connected to said second tap on said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip address control terminal of said timing control network;

a third OR-INVERTER circuit having a first input connected to said read/write input terminal of said timing control network, a second input connected to said first tap on said delay circuit formed by said n serially connected INVERTER circuits, a third input connected to said third tap on said delay circuit formed by said n serially connected delay circuits and an output connected to said on-chip write clock control terminal of said timing control network;

a fourth OR-INVERTER circuit having a first input connected to said output of said single INVERTER circuit, a second input connected to said fourth tap of said delay circuit formed by said n serially connected INVERTER circuits, a third input connected to said output of said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip data output control terminal of said timing control network and, wherein said READ/WRITE memory array is further characterized in that said timing control network further includes;

a test output terminal for providing an off chip test signal; and

,

buffer amplifier circuit means having an input connected to said output of said delay circuit formed by said n serially connected delay circuits and an output connected to said test output terminal of said timing control.

7. In an integrated circuit chip, a memory array, said memory array including:

a plurality of memory elements for storing binary data, said stored binary data being arranged with said array at a plurality of addressable locations;

controllable write circuits means for writing data into said memory array at a predetermined address within said array;

controllable read circuit means for reading data stored in said memory array at a predetermined address within said array;

gated address latch circuit means coupled to said controllable write circuit means and said controllable read circuit means, said gated address circuit means providing said predetermined address to said write circuit means or said read circuit means;

gated data input latch circuit means coupled to said controllable write circuit means, said gated input latch circuit means providing data to be written into said memory array at said predetermined address provided by said address latch circuit means; and

gated data output latch circuit means coupled to said controllable read circuit means, said gated output latch circuit means receiving the binary data read from the memory array as indicated by the predetermined address by said controllable read circuit means;

said integrated circuit chip being further characterized by the inclusion of timing control network circuit means, said timing control network circuit means coupled to and controlling said controllable write circuit means and said controllable read circuit means, said timing control network circuit means also being coupled to said gated address latch circuit means, said gated data input circuit means and said gated data output circuit means, said timing control network on said integrated circuit chip consisting essentially of a serial chain of inverter circuits and said timing control network prividing all timing control signal for the operation of said memory array contained on said integrated circuit chip upon receipt of a trigger signal subsequent to the conditioning of an on chip READ/WRITE control input.