Photosensitive device for the infrared range

• US 4,609,824 A
• Filed: 11/09/1984
• Issued: 09/02/1986
• Est. Priority Date: 11/15/1983
• Status: Expired due to Term

• Current Assignee: Thomson-CSF
• Original Assignee: Thomson-CSF
• Inventors: Arques, Marc, Munier, Bernard
• Primary Examiner(s): Laroche, Eugene R.
• Assistant Examiner(s): Lee, James C.
• Application Number:
  US06/670,409
• Time in Patent Office: 662 Days
• Field of Search: 250/211 J, 250/238, 250/578, 250/352, 250/370 L, 357/32, 358/213
• US Class Current: 348/164
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/779 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

A photosensitive device for the infrared range wherein each detector is connected to a first and a second MOS transistor. The second MOS transistors are addressed, column by column, by a first shift register. The first MOS transistors are connected, line by line, to a charge storage capacity and to a third charge reading MOS transistor addressed by a second shift register. The whole of the device is placed in a cryostat which only has a single output.

Claims

1. A photosensitive device for the infrared range comprising:

an array of N lines and M columns of infrared detectors integrated on a first semiconductor substrate and two electrode arrays, one of the arrays being assigned to the detectors of the same line and the other to the detectors of the same column;

a first MOS transistor connected between each detector and an electrode of the first array;

a first shift register which addresses one after the other the electrodes of the second array, the first MOS transistors and the first register being integrated on a second semiconductor substrate and placed in a cryostat with the detectors, said device further comprising, integrated in the second semiconductor substrate and placed in the cryostat;

a second MOS transistor connected between a gate of each first MOS transistor and an electrode of said second array;

a capacitor, connected between each electrode of the first array and a reference potential, said capacitor serving successively for storing then reading the charges due to the detectors connected to this electrode;

a third MOS transistor connected between each electrode of the first array and the output of the photosensitive device and which allows the charges to be read which are stored in each capacitor;

a second shift register which, when the first register addresses an electrode of the second array, addresses one after the other, the gate of the third MOS transistors connected to an electrode of the first array, as well as the gates of the second MOS transistors controlling the gates of the first MOS transistors connected to another electrode of the first array, which allows all the detectors connected to each electrode of the second array to be read successively and the charges coming from a detector connected to each of the other electrodes of the first array to be integrated when a detector connected to an electrode of the first array is read.

2. The device as claimed in claim 1, wherein the infrared detectors are photodiodes.

3. The device as claimed in claim 1, wherein

the first and second shift registers address successively the electrodes of rank 1, 2, 3 . . . i, i+1, i+2 . . . then again 1, 2, 3, . . . ;

the second shift register addresses the gate of the third MOS transistor connected to the electrode of rank i+1 of the first array and the gates of the second MOS transistors controlling the gates of the first MOS transistors connected to the electrode of rank i of the first array.

4. Device as claimed in claim 2, wherein:

the first and second shift registers address successively the electrodes of rank 1, 2, 3 . . . i, i+1, i+2 . . . then again 1, 2, 3 . . . ;

the second shift register addresses the gate of the third MOS transistor connected to the electrode of rank i+1 of the first array and the gates of the second MOS transistors controlling the gates of the first MOS transistors connected to the electrode of rank i of the first array.