Noise inverter circuit for a power line communication system

• US 4,609,839 A
• Filed: 10/01/1984
• Issued: 09/02/1986
• Est. Priority Date: 10/01/1984
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Howell, Edward K.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/656,804
• Time in Patent Office: 701 Days
• Field of Search: 307/540, 307/542, 307/549, 307/551, 307/555, 307/560, 307/567, 328/54, 328/168, 328/169, 328/171, 328/172, 328/173, 340/310 A
• US Class Current: 327/310
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/5425 improving S/N by matching impedance, noise reduction, gain control
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 3/54 Systems for transmission via power distribution lines

Abstract

A noise inverter circuit substantially reduces the effects of noise generated within power lines operating as a communication media. Input noise signals are clipped to reduce the noise wave amplitude and the peak amplitude is inverted to a value less than the signal amplitude. By limiting the positive rate of change of peak signal amplitude, the prevailing signal level is averaged over a longer time base than the duration of the noise wave.

Claims

1. A noise inverter circuit for a power line communication system comprising:

first and second input terminals for receiving an alternating current electrical communication signal voltage which may include impulse noise;

third and fourth output terminals for providing an output alternating current electrical communication signal voltage, said second input terminal and said fourth output terminal being connected in common;

first and second oppositely polled capacitors each connected at one end thereof to said first input terminal;

first and second diodes each having an anode and a cathode, the cathode of said first diode being connected to the other end of said first capacitor and the anode of said second diode being connected to the other end of said second capacitor;

a first resistor connected at one end to the anode of said first diode and the cathode of said second diode and at the other end to the common connection of said second input terminal and the fourth output terminal, said first and second capacitors charging through said first and second diodes, respectively, and said first resistor to the prevailing peak signal voltage on alternate polarity peaks;

a second resistor connected between said first and second capacitors to provide a discharge path therebetween;

a third resistor connected between said first input terminal and said third output terminal for limiting the peak voltage across said first and second capacitors and reducing the peak output voltage across said third and fourth output terminals; and

first and second transistors of opposite conductivity type each having a base, collector and emitter, the collectors of said first and second transistors being connected in common to said third output terminal, the emitters of said first and second transistors being connected to the common connection of said second input terminal and said fourth output terminal, the base of said first transistor being connected to the cathode of said first diode, and the base of said second transistor being connected to the anode of said second diode, whereby said first and second transistors are biased into conduction on alternate polarity peaks for signal voltages above a predetermined amplitude to thereby invert the peak amplitudes to a value less than the signal amplitude.

2. The noise inverter circuit of claim 1 including first and second diode strings for conducting current of opposite polarities and connected between said first input terminal and said third output terminal for further limiting the peak amplitude of the voltage across said first and second capacitors, said first and second diode strings conducting upon the occurrence of a predetermined level of input voltage.

3. The noise inverter of claim 1 further including a fourth resistor connected at one end to said first input terminal and at the other end to said third resistor and to said first and second resistors for limiting the current to said first and second transistors.

6. The noise inverter of claim 3 further including fourth and fifth resistors connected between the emitters of said third and fourth transistors, respectively, and said common connection of said second input terminal and said fourth output terminal.

4. A noise inverter circuit for a power line communication system comprising:

first and second input terminals for receiving an alternating current electrical communications signal voltage which may include impulse noise;

third and fourth output terminals for providing an output alternating current electrcial communication signal voltage, said second input terminal and said fourth output terminal being connected in common;

an amplifier having an input and an output, the input of said amplifier being connected to said first input terminal;

first and second oppositely polled capacitors each connected at one end thereof to the output of said amplifier;

first and second diodes each having and anode and a cathode, the cathode of said first diode being connected to the other end of said first capacitor and the anode of said second diode being connected to the other end of said second capacitor;

a first resistor connected at one end to the anode of said first diode and the cathode of said second diode and at the other end to the common connection of said second input terminal and the fourth output terminal, said first and second capacitors charging through said first and second diodes, respectively, and said first resistor to the prevailing peak signal voltage on alternate polarity peaks;

a second resistor connected between said first and second capacitors to provide a discharge path therebetween;

a third resistor connected between said first input terminal and said third output terminal for limiting the peak voltage across said first and second capacitors and reducing the peak output voltage across said third and fourth output terminals;

first and second transistors of opposite conductivity type each having a base, collector and emitter, the collectors of said first and second transistors being connected in common to said first input terminal, the emitters of said first and second transistors being connected to the common connection of said second input terminal and said fourth output terminal; and

third and fourth transistors of the same conductivity type as said first and second transistors, respectively, and each having a base, collector and emitter, the collectors of said third and fourth transistors being connected in common to said third output terminal, the emitters of said third and fourth transistors being connected to the common connection of said second input terminal and said fourth output terminal, the bases of said first and third transistors being connected in common to the cathode of said first diode, and the bases of said second and fourth transistors being connected in common to the anode of said second diode, whereby said first and third and said second and fourth transistors are biased into conduction on alternate polarity peaks for signal voltages above a predetermined amplitude to thereby invert the peak amplitudes to a value less than the signal amplitude.

5. The noise inverter of claim 4 wherein said amplifier is an operational amplifier.

7. The noise inverter of claim 4 further comprising a sixth resistor connected between said first input terminal and the input to said amplifier.