Microcomputer with severable ROM

• US 4,609,985 A
• Filed: 12/30/1982
• Issued: 09/02/1986
• Est. Priority Date: 12/30/1982
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: Thomson Components-Mostek Corporation
• Inventors: Dozier, Harold W.
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/454,799
• Time in Patent Office: 1,342 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/189, 365/200, 365/94
• US Class Current: 711/102
• CPC Class Codes: G06F 9/268 Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs

Abstract

A microcomputer has provision for both on-chip ROM (on the same chip as the CPU) and off-chip ROM and which may operate with only on-chip ROM as only off-chip ROM has the hardware capability to disable on-chip ROM permanently, so that chips having defective ROM may be salvaged by being converted to computer chips that use only off-chip ROM.

Claims

1. A single-chip microcomputer comprising:

a central processing unit (100) having at least two alternative memory access modes;

input/output means (104) within said central processing unit (100) and connected to at least one external pin (102) thereof; and

on-chip read-only memory (155) within said central processing unit (100);

which microcomputer includes;

disabling means (150), coupled to said pin (102) and responsive to application of a voltage in excess of 5 volts to said external pin (102) of said microcomputer and having a ROM disable output (152) connected to said on-chip read-only memory (155), to permanently disable said on-chip read-only memory (155), said disabling means including a resistance element (162) of limited current capacity, having first and second terminals, said second terminal being connected to ground and said first terminal being connected to a ROM-disable node (163), said node (163) being connected to a high-current capacity transistor (156) and to said ROM disable output (152), said node (163) being normally held at a predetermined first voltage state by connecting said node (163) to said second, grounded, terminal thereof, whereby said application of a voltage in excess of five volts results in said transistor (156) being gated open and causes said resistance element (162) to be destroyed and said ROM-disable node (163) to change to a second voltage; and

means (170,

     200), connected to said output (152) of said disabling means (150) and to a mode input (172), for accessing external memory.

2. A microcomputer according to claim 1, wherein said at least two modes include

a single-chip mode in which said central processing unit (100) accesses only said on-chip read-only memory (155) and

a fully expanded mode in which said on-chip read-only memory (155) is disabled by said disabling means (150), and said central processing unit (100) accesses external memory.

3. a microcomputer according to claim 2, in which said disabling means (150) responds to a high voltage applied to said external pin (102), of said microcomputer, connected over a first connecting line (106) to an input of

a high voltage detection circuit (110) that applies voltage over a second connecting line (154) to a gate of

said high-current capacity transistor (156) that, in turn, applies a high current to said first terminal of said resistance element (162).

4. A microcomputer according to claim 3, in which

said means (170, 200) for accessing external memory responds to said second voltage on said ROM-disable node (163) in such a manner that any signal on said mode input (172) is rendered ineffective, whereby said memory access mode is forced to one of said at least two modes.