Programmable logic array device using EPROM technology
First Claim
1. A programmable integrated circuit logic array device, comprising:
- a plurality of input terminals for receiving input signals;
a plurality of I/O terminals for receiving input signals and/or transmitting output signals;
a first plurality of macrocells each including at least a first programmable AND array having a first plurality of memory cells arranged in addressable rows and columns, each said cell being individually programmable to contain logic data corresponding to the memory state of the cell, first sensing means connected to said first AND array, said first sensing means being responsive to certain ones of said input signals and operative to detect the memory state of one or more of said cells and to develop a corresponding first data signal, first signal storage means, first feedback means, and first multiplexing means for selectively coupling said first data signal to one of said I/O terminals, to said first storage means, or to said first feedback means; and
a plurality of data buses including a global input signal bus for coupling input signals from said input terminals to a first group of cells in the AND arrays of each said macrocell, a local feedback bus for coupling signals applied to the feedback means of at least some of said macrocells to a second group of cells of at least some of said macrocells, and a global feedback bus for coupling data signals applied to some of said feedback means to a third group of cells of all of said AND arrays of said macrocells.
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Abstract
An electrically programmable, eraseable and reprogrammable, monolithic integrated circuit logic array device is disclosed. The device includes a plurality of three types of logic array macrocells, each including an AND array matrix of EPROM transistors configured to form a plurality of "product terms" which are fed into another matrix comprised of "OR" gates, the outputs of which form sum-of-products expressions of the inputs to the AND arrays. Also contained in the macrocells are simple EPROM transistors which, when combined with other appropriate circuitry, form control elements, a plurality of storage registers (D flip-flops), feedback drivers, input drivers and output drivers, all integrated on the same substrate. The input drivers and feedback drivers provide input signals to the AND arrays and the outputs from the D flip-flops can be directed to either the feedback drivers or the output drivers. Control of data sources and destinations is determined by the control elements which in turn are determined by single EPROM transistors. Thus, the architecture as well as the logic function is programmable.
442 Citations
18 Claims
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1. A programmable integrated circuit logic array device, comprising:
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a plurality of input terminals for receiving input signals; a plurality of I/O terminals for receiving input signals and/or transmitting output signals; a first plurality of macrocells each including at least a first programmable AND array having a first plurality of memory cells arranged in addressable rows and columns, each said cell being individually programmable to contain logic data corresponding to the memory state of the cell, first sensing means connected to said first AND array, said first sensing means being responsive to certain ones of said input signals and operative to detect the memory state of one or more of said cells and to develop a corresponding first data signal, first signal storage means, first feedback means, and first multiplexing means for selectively coupling said first data signal to one of said I/O terminals, to said first storage means, or to said first feedback means; and a plurality of data buses including a global input signal bus for coupling input signals from said input terminals to a first group of cells in the AND arrays of each said macrocell, a local feedback bus for coupling signals applied to the feedback means of at least some of said macrocells to a second group of cells of at least some of said macrocells, and a global feedback bus for coupling data signals applied to some of said feedback means to a third group of cells of all of said AND arrays of said macrocells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification