Decoder for digital information T.V. signal

• US 4,611,227 A
• Filed: 11/22/1982
• Issued: 09/09/1986
• Est. Priority Date: 03/20/1981
• Status: Expired due to Term

• Current Assignee: Independent Broadcasting Authority
• Original Assignee: Independent Broadcasting Authority
• Inventors: Day, Stephen, Brockhurst, David M., Vivian, Roy H., Dyer, Martyn R.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/448,986
• Time in Patent Office: 1,387 Days
• Field of Search: 358/141, 358/142, 358/146, 358/147, 340/723, 340/728
• US Class Current: 348/468
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/222 Control of the character-code memory
• CPC Class Codes: H04N 7/025 Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame transmission of digital non-picture data during the vertical blanking interval only H04N7/088

Abstract

A television receiver is provided with a decoder (32) for decoding and displaying data which is included in a wide band video signal. In order to provide high resolution graphics, a processor (45) is connected to a data page store (41) of the decoder (32) and a program store (47). Instructions for the processor (45) are received `off air` and are stored in the store (41). The instructions are executed using programs stored in the store (47). A clock circuit (45a) is provided for the processor (45) to enable delays and other timed sequences to be introduced and a rounding circuit (46a) ensures as smooth an output display as possible. Data can additionally be received from another soce via a telephone line and selected for display in place of the `off air` data.

Claims

1. In a television system including input means (40) for receiving a demodulated television signal carrying, during picture-free periods thereof, a set of pages of information represented by serial binary signals provided in a repeated cycle and at least some of the binary signals representing coded instructions, the form of the cycle being such that the binary signals for the set of pages received are in groups, which groups are received each in a different one of said periods and the whole of the information for the set of pages is received during each occurrence of the cycle;

a parallel binary memory device (41) connected with the input means (40) for storing binary signals representing a page of information;

processing means (45) for controlling the system and connected with the input means and the parallel binary memory device;

selector means (42) connected with the processing means for generating a desired page address code and activating the processing means to effect storage of the binary signals representing the page;

further storage means (47) connected with the processing means and the parallel binary memory device (41) for storing a plurality of routines for use by the processing means;

the processing means being arranged to access a received coded instruction in the parallel binary memory device and accessing the further storage means in order to carry out the required instruction;

signal generator means (44) connected with the parallel binary memory device (41) for processing the signals stored in the parallel binary memory device to produce output signals for visual display; and

display means (30) connected with the signal generator means (44) for visual display of the signals produced by the signal generator,

the improvement comprising;

(a) a timer means (45a) connected with said processing means (45) for enabling the same to control the timing of the processing of the incoming coded instructions;

(b) inhibiting means (44a) connected with said signal generator means (44) and said processing means (45) and operable by said processing means to prevent operation of the said signal generator; and

(c) auxiliary storage means (48) connected with said signal generator means (44), said parallel binary memory device (41), said further storage means (47) and the said processing means (45) for receiving signals representing a visual image from at least one of the processing means, signal generator means and the parallel binary memory device, said processing means (45) and timer means (45a) being arranged to effect and control the input of signals from said at least one of the processing means (45), signal generator means (44) and parallel binary memory device to the auxiliary storage means (48), said auxiliary storage means (48) having an output connected with said display means (30), thereby to display the contents of said auxiliary storage means.

2. A system according to claim 1, wherein said auxiliary storage means comprises a plurality of storage means (48, 49), said processor means (45) and said timer means (45a) being arranged to feed signals from said plurality of storage means respectively, to a further store.

3. A system as defined in claim 1, wherein said selector means includes control circuit means (42) arranged for response to user input signals indicative of a desired display, said control circuit means (42) being connected with said processing means (45) for inputting control signals to the processing means.

4. A system according to claim 1, and further including means (46a) for interpolating between lines on a display to smooth diagonal transitions.

5. A system according to claim 4, wherein said interpolating means comprises means for delaying the signals representing one line of display, and means for comparing portions of an existing line with corresponding portions of a delayed line, thereby to produce a control signal indicative of whether interpolation should or should not take place.

6. A system according to claim 5, wherein said comparing means is arranged to compare a selected data signal representing a portion of said existing line with a delayed data signal representing an immediately diagonally adjacent portion of said delayed line.

7. A system according to claim 6, wherein said interpolating means comprises means for adding the selected data signal at a time occupied by an immediately preceding or succeeding data signal of the same line.

8. A system according to claim 1, and further comprising means for receiving further digital data in the form of binary signals from a separate channel, and channel selector means (60) for supplying to said memory device (41) said further digital data or said first-mentioned binary signals.

9. A system according to claim 8, wherein separate channel comprises a telephone line.

10. Apparatus as defined in claim 1 and further including transmitter means including transmitter processing means (80, 82, 84, 86, 88) for generating digital signals in the form of coded instructions, and for producing said coded instructions as the set of pages of binary signals, said transmitter processing means including means (80) for digitizing a curve, characterised in that said digitizing means includes means (82,84) for moving a cursor in one of the multiplicity of directions and by a distance indicative of an integer number of display locations.