Programmable testing analyzer

• US 4,611,320 A
• Filed: 05/21/1984
• Issued: 09/09/1986
• Est. Priority Date: 05/21/1984
• Status: Expired due to Fees

• Current Assignee: Siemens Corporate Research & Support, Inc. (Siemens AG)
• Original Assignee: Siemens Corporate Research & Support, Inc. (Siemens AG)
• Inventors: Southard, Gary
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/612,206
• Time in Patent Office: 841 Days
• Field of Search: 370/13, 370/14, 370/15, 370/16, 370/58, 370/85, 179/175.2 D
• US Class Current: 370/241
• CPC Class Codes: H04M 3/244 for multiplex systems
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

The invention relates to a transmission testing arrangement for executing performance tests for a telecommunication system which includes a central switch to the common control unit, a switching network, and line interface units internally connected to the switching network and adapted for connection to a corresponding line circuit. The testing arrangement includes a bus-oriented microprocessor system for synthesizing and analyzing test signals, a program memory, a main memory, and first and second interface modules.

Claims

1. A transmission test arrangement for use with a digital telecommunication system, said system including a central switch having a common control unit including a system bus and controlled by said common control unit, a switching network, and a plurality of line interface units being internally connected to said switching network and each said line interface unit being adapted to be connected to a corresponding line circuit, said test arrangement for executing performance tests on devices of said telecommunication system and comprising:

a bus-oriented microprocessor system designed for synthesizing and analyzing test signals in accordance with a particular algorithm written in a particular signal processing language, including a processor bus, and, residing on said processor bus, a microprocessor, a program memory, a main memory and a first interface module;

said first interface module being connected to said system bus for receiving test control information specifying a test procedure from the common control unit and for transmitting test results to the common control unit;

said main memory and said program memory being designed for storing intermediate data and control information for executing a test, respectively; and

a second interface module for providing an interface between a device of the telecommunication system and the bus-oriented microprocessor system, the second interface module being connected to a selected one of said line interface units for simulating an information source and sink, respectively with respect to one of said devices of the telecommunication system being temporarily linked to said selected line interface unit across the switching network under control of the common control unit, the particular algorithim written in the particular signal processing language permitting control of signal synthesis, signal analysis and signal processing functions of the transmission test arrangement, the transmission test arrangement operating in real time or off line under software control.

2. The transmission test arrangement as recited in claim 1, wherein the digital telecommunication system includes at least two groups of line interface units, first line interface units having an analog input/output port for connection to an analog line circuit, and second line interface units having a digital input/output port adapted to be connected to a line circuit of digital design, and wherein the second interface module of the transmission testing arrangement is connected to a selected one of said second line interface units.

3. The transmission test arrangement as recited in claim 2, wherein said microprocessor system is an input/output processing unit designed for receiving test requests and reporting test results across said first interface module, for initiating tests including synthesis of test signals to be transmitted during a test, and for analyzing signals received from a device under test;

and wherein said second interface module comprises a further microprocessor system, in particular, a signal transfer processing unit operating under control of said input/output processing unit and executing signal transfers to and from the device under test across the line interface unit connected thereto.

4. The transmission test arrangement as recited in claim 3, wherein said signal transfer processing unit includes a signal transfer processing bus, and, residing on said signal transfer processing bus, a processing unit, a main memory, a program memory and a digital interface network being cross-connected to said selected one of said second line interface units.

5. The transmission test arrangement as recited in claim 4, wherein said input/output processing unit and said signal transfer processing unit each comprise a further interface device, each said further interface device residing on the respective bus of the input/output processing unit and the signal transfer processing unit and said further interface devices are cross-connected for providing data transfer between both processing units.

6. The transmission test arrangement as recited in claim 5, wherein said signal transfer processing unit being designed to utilize a dedicated area of main memory of the input/output processing system includes a memory decoder connected to receive a memory address across the signal transfer processing bus for decoding said memory address into an address of the signal transfer processing unit'"'"'s main and program memories and said dedicated memory area, respectively;

and wherein said memory decoder is connected to main and program memories of the signal transfer processing unit and across said two further interface devices to the microprocessor of the input/output processing unit for requesting access to said dedicated memory area by means of a direct memory access routine.

7. The transmission test arrangement as recited in claim 2, wherein the bus-oriented microprocessor system comprises storage means constructed in the form of buffers of predetermined lengths utilized for intermediately storing signal patterns in a manner corresponding to real-time processing conditions of the telecommunication system, whereby a buffer length reflects an actual time period based upon the assumption that the buffer during execution of a test is filled and emptied, respectively byte-by-byte with the sampling rate of the telecommunication system.

8. The transmission test arrangement as recited in claim 7, in conjunction with a telecommunication system operating on a sampling rate of 8 KHz, wherein said buffers each are identified by an individual buffer name and are further defined by an individual length variable expressed in milliseconds, said buffer name is interpreted by the microprocessor system into a microprocessor memory address of the first byte of the buffer and said length variable determines the number of subsequent bytes of the storage area allocated to said buffer and eight bytes of memory correspond to one millisecond of a time interval.

9. The transmission test arrangement as recited in claim 7, wherein said microprocessor system being designed to operate under software control based upon test programs of the particular algorithm represented in the particular signal processing language, in particular, a high level language, translated by compiler into data base and each test program providing an individual test array constituting the sum of statements describing a test, includes:

means for controlling input/output operations in order to receive a test array and report test results, respectively;

means for interpreting the statements of the test array received in order to define buffers, tables and registers required for executing the respective test by allocating corresponding memory areas thereto and to generate an operational code for executing the corresponding statement, respectively; and

means for executing operational codes supplied by said interpreting means for providing signal synthesis and signal analysis, respectively in accordance with parameters and variables defined in the respective test program, said executing means being furthermore designed to transfer control to the signal transfer processing unit for activating the signal transfer processing unit to actually transfer test signals under real-time conditions.

10. The transmission test arrangement as recited in claim 2, wherein said microprocessor system for synthesizing test signals includes means for generating signals of frequency sinusoids with a predetermined power level, said signals being represented in a linear digital format of at least twelve bits plus a sign bit and means for transforming said linear signal representations into a companded format in accordance with A law and Mu law, respectively.

11. The transmission test arrangement as recited in claim 10, wherein said signal generating means are designed to include sinusoidal signals of a frequency up to at least 4 KHz with a power level to be selected in the range from -60 dbm to at least 3.1 dbm.

12. The transmission test arrangement as recited in claim 11, wherein said signal generating means are designed to generate modulated signals out of any combination of those sinusoidal signals.

13. The transmission test arrangement as recited in claim 12, wherein said signal generating means include means for generating pulsed tones and pulsed tone combinations, respectively with predetermined pulse widths and idle tone intervals to be set in steps of one millisecond each.

14. The transmission test arrangement as recited in claim 13, wherein said means for generating pulsed tones and pulsed tone combinations include means for generating linear ramps at rise and fall of each pulse edge.

15. The transmission test arrangement as recited in claim 14, wherein said signal generating means are furthermore designed to generate a sequence of pulse code modulated (PCM) code words commonly representing all possible digit combinations of samples transmitted within said telecommunication system.

16. The transmission test arrangement as recited in claim 2, wherein the microprocessor system for analyzing signals received by the test arrangement from a device under test comprises means for filtering said signals received, said filter means implementing digital filters including band pass, high pass, low pass and notch filters;

and means for digitally measuring the power level of said signals received.

17. The transmission test arrangement as recited in claim 16, wherein said filter means are designed to provide said filter types with presettable characteristics by means of individually specified filter parameters.

18. The transmission test arrangement as recited in claim 2, the microprocessor system for analyzing signals received further comprising means for analyzing envelopes of tone pulses including measurements of pulse period, duty cycle and rise and fall times of pulse edges.

19. The transmission test arrangement as recited in claim 18, in conjunction with a telecommunication system providing a specific pulse code word for representing an idle tone sample, wherein said envelope analyzing means further include means for recognizing the pulse code word representing idle tone.

20. The transmission test arrangement as recited in claim 2, wherein the microprocessor system for analyzing said signals received further comprises means for comparing measured values of said signals received to conditional parameter values specified for the respective test.

21. The transmission test arrangement as recited in claim 20, wherein the said comparison means are further designed to provide comparison of a signal received to a reference signal on a byte-by-byte basis.

22. The transmission test arrangement as recited in claim 9, wherein the second interface module is designed to be connected in parallel to a plurality of said second line interface units each providing a separate transmission path to a selected device under test whereby a plurality of tests can be run simultaneously.

23. The transmission test arrangement as recited in claim 22, wherein, in order to provide for interleaving of simultaneously performed tests, said means for executing operational codes include means for controlling the course of a test by means of continuously assigning a respective test state to each specific line interface unit connected to the test arrangement in such a manner that each test state is associated with a specific type of operation of the microprocessor system and only specific sequences of states are made possible in dependence upon the progress of the respective test and the test states of the remaining line interface units.

24. The transmission test arrangement as recited in claim 23, wherein a normal sequence of said test states includes in consecutive order:

an idle state representing the respective line interface unit being available for assigning a new test;

a start state representing the active condition of said means controlling input/output operations;

an active state being assumed when the microprocessor system is performing signal synthesis and analysis, respectively;

a suspended state representing actual transfer of test data to and from the device under test by means of said second interface module;

a wait state representing completion of test data transfer prior to signal analysis and being terminated by a return to said active state for signal analysis;

a completed state representing the course of a test when test results including test failures are available to be sent out, said state being terminated after reporting test results by return to idle state; and

wherein furthermore a conditional transition from suspended state to completed state takes place in case of a detected failure with respect to input/output operations across the respective line interface unit.

25. The transmission test arrangement as recited in claim 1, wherein the common control of the telecommunication system is a bus-oriented central processing system having a system bus and including input/output processing modules each forming a sub-system of the common control unit and wherein said first interface module comprises an interface unit connected to said system bus, whereby the transmission test arrangement constitutes a sub-system of said common control unit.

26. The transmission test arrangement as recited in claim 24, wherein the testing arrangement shares a common central memory area with said central processing system and has access to this common central memory area by means of a direct memory access routine whereby test arrays are down-loaded from common control to the test arrangement.

27. The transmission test arrangement as recited in claim 25, in conjunction with the common control unit further including a stand-by central processing system for redundancy, wherein said first interface module is duplicated in said microprocessor system in order to provide separate interface means to both central processing systems, whereby the test arrangement constitutes a sub-system alternatively utilized by either one of the central processing systems.