Process of fabricating three-dimensional semiconductor device

• US 4,612,083 A
• Filed: 07/17/1985
• Issued: 09/16/1986
• Est. Priority Date: 07/20/1984
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hayama, Hiroshi, Enomoto, Tadayoshi, Yasumoto, Masaaki
• Primary Examiner(s): Powell, William A.
• Application Number:
  US06/755,987
• Time in Patent Office: 426 Days
• Field of Search: 156/633, 156/634, 156/643, 156/644, 156/646, 156/653, 156/656, 156/657, 156/659.1, 156/668, 156/307.3, 156/313, 430/313, 430/314, 430/315, 430/317, 430/318, 427/38, 427/39, 427/88-91, 357/65, 357/71, 29/571, 29/576 R, 29/576 W, 29/576 J, 29/578, 29/588, 29/591, 148/1.5, 148/187
• US Class Current: 438/59
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/73104 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/80357 being flush with the surface
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/81121 Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: Y10S 148/164 : Three dimensional processing

Abstract

A process of fabricating a three-dimensional semiconductor device, comprising the steps of preparing at least two multilayer structures each including at least one semiconductor element and a conductor connected at one end to the semiconductor element and having at the other end an exposed surface, at least one of the multilayer structures further including a thermally fusible insulating adhesive layer having a surface coplanar with the exposed surface of the conductor, positioning the multilayer structures so that the exposed surfaces of the respective conductors of the multilayer structures are spaced apart from and aligned with each other, moving at least one of the multilayer structures with respect to the other until the exposed surfaces of the conductors of the multilayer structures contact each other, and heating the multilayer structures for causing the insulating adhesive layer of at least one of the multilayer structures to thermally fuse to the other multilayer structure with the semiconductor elements electrically connected together.

Claims

1. A process of fabricating a three-dimensional semiconductor device, comprising the steps of

(1) preparing at least two semiconductor structures each including at least one semiconductor element and a conductor electrically connected at one end to said semiconductor element and having at the other end thereof an exposed surface portion, at least one of said semiconductor structures further including a thermally fusible insulating adhesive layer having a surface substantially coplanar with said exposed surface of said conductor,

(2) positioning said semiconductor structures with respect to each other so that the exposed surface portions of the respective conductors of the semiconductor structures are spaced apart from and substantially aligned with each other,

(3) moving at least one of said semiconductor structures with respect to the other until the exposed surface portions of the respective conductors of the semiconductor structures are brought into contact with each other, and

(4) heating the semiconductor structures for causing said insulating adhesive layer of at least one of said semiconductor structures to thermally fuse to the other semiconductor structure with said semiconductor elements electrically connected together.

2. A process as set forth in claim 1, in which the semiconductor structure including said insulating adhesive layer is prepared by

(1) forming on a substrate a functional layer containing said semiconductor element therein,

(2) forming an insulating layer overlying said functional layer for covering the semiconductor element in the functional layer,

(3) forming said conductor extending in part in said insulating layer and, the conductor being electrically connected at one end to said semiconductor element and having said exposed surface portion protruding from the surface of the insulating layer, and

(4) forming said insulating adhesive layer on said insulating layer so that said conductor is in part embedded in the insulating adhesive layer and has its exposed surface portion substantially coplanar with the surface of the insulating adhesive layer.

3. A process as set forth in claim 2, in which said conductor in the semiconductor structure including said insulating adhesive layer is formed by

(1) forming an opening in said insulating layer with a patterned photoresist coating formed on the insulating layer,

(2) depositing an electrically conductive material in said opening and on said photoresist coating for forming a conductive layer thicker than said insulating layer and electrically connected to said semiconductor element, and

(3) removing said photoresist coating and that portion of the conductive layer which overlies the photoresist coating from said insulating layer for thereby forming said conductor.

4. A process as set forth in claim 2, in which said insulating adhesive layer is formed by

(1) spin coating the surface of said insulating layer with a dielectric adhesive substance rotating the semiconductor structure including said insulating layer for forming a coating of the dielectric adhesive substance to a thickness greater than the height which said conductor protrudes from the surface of said insulating layer, and

uniformly etching the coating of the dielectric adhesive substance to a depth which is uniform substantially throughout its area for causing said exposed surface to appear on a plane substantially flush with the surface of the resultant insulating adhesive layer.

5. A process as set forth in claim 1, in which at least one of said semiconductor structures includes a plurality of functional layers each containing a semiconductor element therein, an insulating layer intervening between adjacent two of the plurality of functional layers, and a conductive element extending through said insulating layer and interconnecting the semiconductor elements in the adjacent functional layers.

6. A process as set forth in claim 1, in which each of said semiconductor structures includes a plurality of functional layers each containing at least one semiconductor element therein, an insulating layer intervening between adjacent two of the plurality of functional layers, and a conductive element extending through said insulating layer and interconnecting the semiconductor elements in the adjacent functional layers.

7. A process as set forth in claim 5 or 6, in which said plurality of functional layers include first and second functional layers and in which the semiconductor structure including the first and second functional layers is prepared by

(1) forming the first functional layer on a substrate,

(2) depositing said insulating layer on the first functional layer as a first insulating layer for covering the semiconductor element contained in the first functional layer,

(3) forming the second functional layer by forming a monocrystalline semiconductor film forming at least one semiconductor element electrically connected to the semiconductor element in said first functional layer across said first insulating layer,

(4) forming a second insulating layer on said second functional layer, and

(5) forming said conductor extending through said second insulating layer, the conductor being connected at one end to the semiconductor element in said second functional layer and having said exposed surface portion substantially coplanar with the surface of the second insulating layer.

8. A process as set forth in claim 6, in which said semiconductor structures are prepared by

(1) forming a first semiconductor structure including (a) a first functional layer formed on a substrate and containing at least one semiconductor element therein, (b) a second insulating layer formed on the first functional layer and covering the semiconductor element in the functional layer, (c) an insulating adhesive layer formed on the insulating layer, and (d) a first conductor extending through said insulating layer and said insulating adhesive layer, the first conductor being electrically connected at one end to the semiconductor element in said first functional layer and having an exposed surface portion substantially flush with the surface of the first insulating adhesive layer;

and a second semiconductor structure including (e) a second functional layer formed on a substrate and containing at least one semiconductor element therein, (f) a second insulating layer formed on the second functional layer and covering the semiconductor element in the functional layer, (g) an insulating adhesive layer formed on the insulating layer, (h) a second conductor extending through said insulating layer and said insulating adhesive layer, the second conductor being electrically connected at one end to the semiconductor element in said second functional layer and having an exposed surface portion substantially flush with the surface of the second insulating adhesive layer, and (i) a third conductor extending through said second functional layer and electrically connected at one end to the semiconductor element in said second functional layer, the third conductor having the other end thereof located at the interface between the substrate and the second functional layer and being electrically isolated from said second functional layer,

(2) positioning the first and second semiconductor structures with respect to each other so that the respective insulating adhesive layers thereof are spaced apart from each other,

(3) locating the first and second semiconductor structures with respect to each other so that the respective exposed surface portions of the first and second conductors are substantially aligned with each other,

(4) moving at least one of said first and second semiconductor structures with respect to the other until the respective exposed surface portions of said first and second conductors of the semiconductor structures are brought into contact with each other,

(5) heating the first and second semiconductor structures at a temperature which will substantially not affect the performance characteristics of the semiconductor element in each of the semiconductor structures, for causing said first and second insulating adhesive layers of the semiconductor structures to thermally fuse to each other with the semiconductor elements in the first and second semiconductor structures electrically connected together, and

(6) removing the substrate from said second semiconductor structure for allowing said third conductor to be exposed at one end thereof from said second functional layer.

9. A process as set forth in claim 8, in which said first and second semiconductor structures are forced against each other while being heated to be caused to thermally fuse to each other.

10. A process as set forth in claim 1, in which said semiconductor structures are forced against each other while being heated to be caused to thermally fuse to each other.

11. A process as set forth in claim 1, in which the semiconductor element in one of said semiconductor structures is constituted by an n-type MOS transistor and the semiconductor element in the other semiconductor structure is constituted by a p-type MOS transistor.

12. A process as set forth in claim 1, in which the semiconductor element in one of said semiconductor structures is constituted by an optoelectric transducer element.

13. A process as set forth in claim 1, in which said semiconductor element in one of said semiconductor structures is constituted by a compound semiconductor device and the other semiconductor structure is constituted by a silicon semiconductor device.

14. A process as set forth in claim 1, in which said dielectric adhesive substance consists of a polyimide resin.

15. A process as set forth in claim 3, in which said electrically conductive material consists of gold.