High speed buffer circuit particularly suited for use in sample and hold circuits

• US 4,612,464 A
• Filed: 01/25/1984
• Issued: 09/16/1986
• Est. Priority Date: 01/28/1983
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ishikawa, Fumio, Tanaka, Kuninobu
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US06/573,636
• Time in Patent Office: 965 Days
• Field of Search: 307/352, 307/353, 307/570, 307/443, 307/491, 307/493, 307/494, 307/495, 307/496, 307/497, 307/500, 307/264, 307/270, 307/246, 307/552, 307/553, 307/558, 307/255, 328/115
• US Class Current: 327/333
• CPC Class Codes: H03F 1/307 in push-pull amplifiers
• CPC Class Codes: H03F 3/50 Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower

Abstract

A buffer circuit includes a main buffer circuit section formed of a pair of complementary input side transistors the bases of which are connected together to an input, a dummy circuit section having the same circuit construction as the main buffer circuit section, and a feedback signal section compares the output from the dummy circuit section with a predetermined value to provide a feedback signal which is supplied to the dummy circuit section and the main buffer circuit section so as to make the output of the dummy circuit section equal to that predetermined value.

Claims

1. A high input impedance circuit comprising:

main buffer circuit means, dummy circuit means and feedback circuit means;

each of said main buffer circuit means and said dummy circuit means including a first pair of NPN and PNP transistors and a second pair of NPN and PNP transistors, each of said transistors having a base, emitter and collector, said bases of said first pair of transistors being connected to each other, said emitters of said second pair of transistors being connected to each other, said emitters of said PNP and NPN transistors of said first pair being connected to said bases of said NPN and PNP transistors, respectively, of said second pair, and first and second constant current circuits connected to said emitters of said PNP and NPN transistors, respectively, of said first pair;

power source means of first and second opposed polarities connected to said collectors of said NPN and PNP transistors, respectively, of each of said first and second pairs of transistors;

input means connected to the connected together bases of said first pair of transistors of said main buffer circuit means;

output means connected to the connected together emitters of said second pair of transistors of said main buffer circuit means; and

said feedback circuit means includes first and second constant current source circuits for driving said first and second constant current circuits, respectively, of said main buffer circuit means and of said dummy circuit means, and control circuit means for controlling an amount of a current of at least one of said first and second constant current source circuits so as to achieve substantial equality of a voltage at the connected together emitters of said second pair of transistors in said dummy circuit means with a reference voltage and thereby causing the voltage at said output means to vary with any voltage changes at said input means without requiring any current flow from said input means.

2. A high input impedance circuit comprising:

first and second buffer circuits;

each of said buffer circuits including a first pair of NPN and PNP transistors each having a base, emitter and collector and a second pair of NPN and PNP transistors each having a base, emitter and collector, said bases of the first pair of transistors being connected to each other, said emitters of the second pair of transistors being connected to each other, said emitters of said PNP and NPN transistors of said first pair being connected to said bases of said NPN and PNP transistors, respectively, of said second pair, and first and second constant current circuits which are respectively connected to said emitters of said first pair of PNP and NPN transistors;

power source means to which said collectors of said NPN and PNP transistors of the first and second buffer circuits are connected;

input means connected to the connected together bases of said first pair of transistors of said first buffer circuit;

output means connected to said connected together emitters of said second pair of transistors of said first buffer circuit;

first and second constant current source circuits for driving said first and second constant current circuits of said first and second buffer circuits respectively; and

a control circuit for controlling an amount of a current of at least one of said first and second constant current source circuits including a differential amplifier having first and second input terminals connected to the emitters of said second pair of NPN and PNP transistors of said second buffer circuit and to a source of a predetermined voltage potential, respectively, and an output terminal of said differential amplifier being connected to at least one of said first and second constant current source circuits.

3. A high input impedance circuit according to claim 2, further comprising a capacitor which is connected between said input means and a common terminal.