Hierarchical, computerized design of integrated circuits
First Claim
1. In a computer process for designing an IC by composing a semiconductor chip having a chip from a plurality of basic cells, each selected from a family of basic cells in which each cell conforms to a first common basic cell interconnection format which enables said computer process to arrange a plurality of said cells in a row and which defines the locations in said cell to which said process must to able to route conductors in the process of designing said IC, chip format being different from said basic cell interconnection format, the improvement comprising the steps of:
- (a) composing an arrangement of a plurality of said basic cell to define a higher order building block cell conforming to a second common basic cell interconnection format, like said first common basic cell interconnection format but with larger overall dimensions; and
(b) performing step (a) a plurality of times to create a family of said higher order building block cells each of which conforms to said second common basic cell interconnection format whereby said higher order buidling block cells are themselves composible in the same manner by said computer process into still higher order structures.
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Abstract
High gate count integrated circuits (ICs) are designed in a heirarchical manner. In a first pass through a computer design system basic cells are composed to form one-level-up building block cells. In a second pass through the same computer design system the one-level-up building block cells are used as "basic" cells and composed to form a two-level-up structure which may be a building block cell or a chip.
120 Citations
16 Claims
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1. In a computer process for designing an IC by composing a semiconductor chip having a chip from a plurality of basic cells, each selected from a family of basic cells in which each cell conforms to a first common basic cell interconnection format which enables said computer process to arrange a plurality of said cells in a row and which defines the locations in said cell to which said process must to able to route conductors in the process of designing said IC, chip format being different from said basic cell interconnection format, the improvement comprising the steps of:
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(a) composing an arrangement of a plurality of said basic cell to define a higher order building block cell conforming to a second common basic cell interconnection format, like said first common basic cell interconnection format but with larger overall dimensions; and (b) performing step (a) a plurality of times to create a family of said higher order building block cells each of which conforms to said second common basic cell interconnection format whereby said higher order buidling block cells are themselves composible in the same manner by said computer process into still higher order structures. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A computer process comprising the steps of:
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employing a computerized design system to compose, from a family of basic cells each of which conforms to a first common basic cell interconnection format, a family of building block cells each of which is one hierarchical level up from said basic cells and which conforms to a second common basic cell interconnection format like said first common basic cell interconnection format but with larger overall dimensions; and employing said computerized design system to compose, from said family of one-level-up building block cells a structure which is two hierarchical levels up from said basic cells. - View Dependent Claims (13, 14, 15)
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16. A computer process for designing an integrated circuit chip comprising:
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composing an arrangement of a plurality of building block cells from a first family of building block cells in which each building block cell conforms to a first common basic cell interconnection format to define a building block cell of a second, higher order family of building block cells in which each building block cell conforms to a second common basic cell interconnection format like said first common basic cell interconnection format, but with larger overall dimensions; performing said composing step a plurality of times to create a plurality of said building block cells in said second, higher order, family; and recycling said second family of building block cells through said design system to compose said integrated circuit chip from said building block cells of said second family.
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Specification