Write clock pulse generator used for a time base corrector

• US 4,613,827 A
• Filed: 07/24/1985
• Issued: 09/23/1986
• Est. Priority Date: 07/28/1984
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Abe, Hitoshi, Nakamura, Yoshiyuki, Takamori, Tsutomu
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US06/758,341
• Time in Patent Office: 426 Days
• Field of Search: 331/1 A, 331/20, 331/25, 331/27, 331/2, 358/319, 358/326, 358/19, 360/37.1, 360/51, 360/36.1, 360/36.2
• US Class Current: 331/20
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H04N 9/896 using a digital memory with independent write-in and read-out clock generators

Abstract

A write clock pulse generator is disclosed, in which a horizontal synchronizing signal is separated from an input video signal and supplied to a PLL (phase locked loop) circuit to form a first clock with the frequency of nf_H (n is an integer), a color burst signal is separated from the input video signal and used to drive a gate type variable oscillator to thereby form a second clock synchronized in phase with the color burst signal and whose average frequency is nf_H, a difference between the pulse widths of the clocks resulting from counting down the first and second clocks to 1/M and the frequency of the variable oscillator is controlled by the compared output therebetween, whereby to produce a second clock synchronized in phase with the color burst signal and the frequency of which is n times the horizontal synchronizing signal.

Claims

1. A write clock pulse generator for a time base corrector having a phase locked oscillator responsive to a horizontal synchronizing pulse derived from a reproduced video signal for generating a first clock pulse having a time axis change same as that of said horizontal synchronizing pulse, a frequency of said first clock pulse being n times (n is an integer) the frequency of said horizontal synchronizing pulse, a burst signal separating circuit for separating a color burst signal from said reproduced video signal, and a generating circuit responsive to said first clock pulse and said separated color burst signal for generating a write clock pulse, the phase and frequency of which are locked to those of said separated color burst signal and said horizontal synchronizing pulse, respectively comprising:

(a) a pulse signal generator responsive to said color burst signal for generating a control pulse signal having a pulse width corresponding to a predetermined wave length of said color burst signal, said control pulse signal being in phase with said color burst signal;

(b) a start-stop oscillator responsive to generation of said control pulse signal for generating a second clock pulse the phase of which is in phase with said control pulse signal;

(c) first and second frequency dividers connected to said phase locked oscillator and said start-stop oscillator and for frequency-dividing said first and second clock pulses;

(d) a synchronous circuit responsive to generation of said control pulse for synchronizing dividing operations of said first and second frequency dividers;

(e) a comparator for comparing pulse widths of output pulses of said first and second frequency dividers; and

(f) a control circuit responsive to an output signal of said comparator for controlling a frequency of said start-stop oscillator.

2. The write clock pulse generator according to claim 1, in which a dividing ratio of said first frequency divider is equal to that of said second frequency divider.

3. The write clock pulse generator according to claim 2, in which said comparator is a charge pump type comparator.

4. The write clock pulse generator according to claim 3, in which said charge pump type comparator includes a couple of inverters and AND gates, said output pulse of said first frequency divider is applied to one of said inverters and AND gates, said output pulse of said second frequency divider is applied to the other of said inverters and AND gates, output signals of said inverters are connected to said AND gates, respectively and first and second current sources for charging and discharging a capacitor in response to output signals of said couple of AND gates.