Data encoding and decoding scheme

• US 4,613,913 A
• Filed: 09/05/1984
• Issued: 09/23/1986
• Est. Priority Date: 09/05/1984
• Status: Expired due to Term

• Current Assignee: Tele Atlas North America (TomTom NV)
• Original Assignee: Etak, Inc. (TomTom NV)
• Inventors: Phillips, Alan C.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US06/648,002
• Time in Patent Office: 748 Days
• Field of Search: 360/40, 360/41, 360/51
• US Class Current: 360/51
• CPC Class Codes: G11B 20/10 Digital recording or reproducing
• CPC Class Codes: G11B 20/12 Formatting, e.g. arrangement of data block or words on the record carriers within interface between computers and data recorders G06F3/06

Abstract

Digital data formatted on a data storage medium, in which the medium has a plurality of bit cells and the data format is such that groups of n data bits of an N-bit data word are stored over n consecutive bit cells, respectively, and a clock information bit is stored between the groups at every n+1 bit cell. A decoding apparatus includes circuitry for reading the digital data and producing an analog signal corresponding to the n data bits and the clock information bit, circuitry for reconstructing the digital data in response to the analog signal, and circuitry for producing data-ready pulses at a time corresponding to the bit cells storing the n data bits and for inhibiting the data-ready pulses at a time corresponding to the bit cell storing the clock information bit.

Claims

1. Apparatus for decoding digital data stored on a data storage medium, the digital data including a NRZ data word having groups of n data bits, each group being stored over n consecutive bit cells, respectively, and including a clock information bit stored between said groups at every n+1 bit cell, comprising:

(a) means for reading the digital data stored on the data storage medium and for producing an analog signal corresponding to the n data bits and the clock information bit, wherein the analog signal has positive and negative levels;

(b) means for outputting the digital data in response to the analog signal, including

(i) means for generating a reference signal tracking the average of the positive and negative levels of the analog signal; and

(ii) means for comparing the analog signal with the reference signal and for generating output pulses upon transitions, respectively, of the analog signal going above or below the reference signal, the output pulses being the outputted digital data; and

(c) means, responsive to the digital data being outputted, for producing data-ready pulses at a time corresponding to the bit cells storing the n data bits and for inhibiting the data-ready pulses at a time corresponding to the bit cell storing the clock information bit.

2. Apparatus, according to claim 1, wherein said means for generating a reference signal comprises:

(a) first means for sampling the positive levels of the analog signal to provide a sampled positive level signal;

(b) second means for sampling the negative levels of the analog signal to provide a sampled negative level signal; and

(c) means for summing and averaging the sampled positive level signal and the sampled negative level signal.

3. Apparatus, according to claim 1 wherein said first means for sampling comprises:

(a) a positive level sampler; and

(b) means, responsive to the output pulses, for generating enabling signals to enable said positive level sampler.

4. Apparatus, according to claim 1, wherein said second means for sampling comprises:

(a) a negative level sampler; and

(b) means, responsive to the output pulses, for generating enabling signals to enable said negative level sampler.

5. Apparatus for decoding digital data stored on a data storage medium, the digital data including a NRZ data word having groups on n data bits, each group being stored over n consecutive bit cells, respectively, and including a clock information bit stored between said groups at every n+1 bit cell, comprising:

(a) means for reading the digital data stored on the data storage medium and for producing an analog signal corresponding to the n data bits and the clock information bit;

wherein the analog signal has positive and negative levels;

(b) means for outputting the digital data in response to the analog signal; and

(c) means, responsive to the digital data being outputted, for producing data-ready pulses at a time corresponding to the bit cells storing the n data bits and for inhibiting the data-ready pulses at a time corresponding to the bit cell storing the clock information bit, including

(i) means for generating transition pulses upon the transitions of the analog signal between the positive and negative levels;

(ii) controllable means for producing a pulse train waveform in response to the transition pulses;

(iii) means for generating the data-ready pulses in response to the pulse train waveform; and

(iv) means for detecting each clock information bit in response to the pulse train waveform, said detecting means disabling said data-ready pulse generating means upon detecting the clock information bit and enabling said data-ready pulse generating means in the absence of detecting each clock information bit.

6. Apparatus, according to claim 5, wherein said controllable means for producing a pulse train waveform comprises:

(a) a voltage controlled oscillator for generating the pulse train waveform;

(b) means for generating an enabling signal at a time related to the occurrence of each clock information bit; and

(c) means, enabled in response to the enabling signal, for detecting which pulse occurs first between one of the transition pulses and one of the pulses of the pulse train waveform to produce an error signal, said voltage controlled oscillator being controlled in response to the error signal, and said voltage controlled oscillator resetting the pulse train waveform upon the absence of one of the transition pulses within a maximum time or resetting the pulse train waveform in response to the occurrence of one of the pulses within the maximum time.

7. Apparatus for decoding NRZT digital data stored on a magnetic data storage tape usable in a high shock and vibration environment, the magnetic data storage tape having a plurality of bit cells and the NRZT digital data including an NRZ data word having at least one group of n data bits stored over n consecutive bit cells, respectively, in which n≧

2, and a clock information bit stored between each group of n data bits at every n+1 bit cell, the clock information bit having a logic level transition so that the logic level of the clock information bit is the opposite of the logic level of the data bit of the bit cell next preceding the clock information bit, the apparatus comprising;

(a) means for reading the NRZT digital data stored on the magnetic data storage tape and for producing an analog signal corresponding to the NRZT digital data, the analog signal having positive and negative levels;

(b) means for reconstructing the NRZT digital data stored on the tape in response to the analog signal, including

(i) means for generating a reference signal tracking the average of the positive and negative levels of the analog signal; and

(ii) means for comparing the analog signal with the reference signal and for generating output logical 1 level and logical 0 level pulses upon transitions, respectively, of the analog signal going above and below the reference signal, the output logical pulses being substantially the same as the NRZT digital data; and

(c) means, responsive to the output logical pulses, for producing data-ready pulses at a time corresponding to the bit cells storing the n data bits and for inhibiting the data-ready pulses at a time corresponding to the bit cells storing the lock information bit, including

(i) means for generating transition pulses upon the transitions of the analog signal between the positive and negative levels;

(ii) controllable means for producing a pulse train waveform in response to the transition pulses;

(iii) means for generating the data ready pulses in response to the pulse train waveform; and

(iv) means for detecting each clock information bit in response to the pulse waveform, said detecting means disabling said data ready pulse generating means upon detecting each clock information bit and enabling said data ready pulse generating means in the absence of detecting each clock information bit.

8. Apparatus, according to claim 7, wherein said means for generating a reference signal comprises:

(a) a positive level sampler for sampling the positive levels of the analog signal to provide a sampled positive level signal;

(b) a negative level sampler for sampling the negative levels of the analog signal to provide a sampled negative level signal;

(c) a transition pulse generator, responsive to the output pulses, for generating enabling signals to enable said positive level sampler and said negative level sampler, respectively; and

(d) a summer for averaging the sampled positive level signal and the sampled negative level signal.

9. Apparatus, according to claim 7, wherein said controllable means for producing a pulse train waveform comprises:

(a) a phase resettable voltage controlled oscillator for outputting the pulse train waveform at a controlled pulse repetition frequency;

(b) a clock transition detector for generating an enabling signal at a time related to the time of occurrence of each clock information bit; and

(c) a timing error detector, being enabled in reponse to the enabling signal, for producing an error signal in response to an earlier pulse between one of the transition pulses of said pulse transition generating means and one of the pulses of the pulse train waveform, the controlled pulse repetition frequency of said resettable voltage controlled oscillator being adjustable in response to the error signal.

10. Apparatus, according to claim 9, wherein said clock transition detector comprises a modulo counter.

11. Apparatus, according to claim 7, wherein said modulo counter is a modulo 3 counter.

12. Apparatus, according to claim 7, wherein the magnetic data storage tape further stores a plurality of synchronization bits stored, respectively, over a plurality of the bit cells, and wherein said means for detecting each clock information bit is synchronized in response to the plurality of synchronization bits.