Teletext receiver

• US 4,614,972 A
• Filed: 02/15/1984
• Issued: 09/30/1986
• Est. Priority Date: 02/22/1983
• Status: Expired due to Fees

• Current Assignee: Etablissement Public de Diffusion DIT "Telediffusion de France", L'Etat Francais Represente PAR Le Ministre Des PTT
• Original Assignee: Etat Francais
• Inventors: Sechet, Claude, Motsch, Roger
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Parker, Michael D.
• Application Number:
  US06/580,535
• Time in Patent Office: 958 Days
• Field of Search: 358/142, 358/146, 358/147
• US Class Current: 348/468
• CPC Class Codes: H04N 7/0882 for the transmission of character code signals, e.g. for teletext circuits for the digital non-picture data signal H04N7/035

Abstract

A teletext receiver incorporating a demodulation circuit, a data demultiplexing circuit, a memory, a microprocessor and a numbering keyboard. The inventive receiver also comprises an early article acquisition decision circuit disposed between the demultiplexing circuit and the memory. This circuit incorporates a shift register with five cells, a storage module having a first group of three storage cells able to store three bytes, a second group of three storage cells able to store three bytes, a two-bit flip-flop, a logic comparison circuit incorporating a first group of three byte comparators, a second group of three byte comparators, an article start code detector, and a comparison synthesis logic circuit connected to the six byte comparators, to the detector and to the flip-flop. This circuit supplies an opening or closing control signal applied to the control input of the memory. The microprocessor loads in an appropriate manner the storage cells with bytes defining a page to be selected and bytes defining a threshold, such that all the articles whose classification bytes exceed this threshold, bring about the appearance of the memory opening signal. The microprocessor checks after each data transmission cycle the state of the memory in order to raise or lower the threshold, or leave it unchanged.

Claims

1. A teletext receiver comprising:

a demodulation circuit having an input receiving a composite signal resulting from multiplexing between digital data and a video signal and an output supplying the digital data only,

a data demultiplexing circuit having an input connected to the output of the demodulation circuit and an output supplying digital data along continuous channels, said data being organized into articles, each article incorporating an article start constituted by two special codes, followed by an article heading having, inter alia, three classification bytes C1, C2 and C3,

memory having a digital data input and a control input,

a microprocessor,

a numbering keyboard for choosing a three-byte code, said code being between 001 and 999,

wherein it also comprises an early article acquisition decision circuit inserted between the demultiplexing circuit and the memory, said circuit incorporating;

a shift register having a series input connected to the demultiplexing circuit, a series output connected to the data input of the memory, said register having three first cells containing respectively, said three classification bytes C₁, C₂ and C₃ and two other cells containing said two special codes connected to five parallel outputs,

a storage module having a first group of three storage cells able to store three bytes, namely A₁, A₂ and A₃, a second group of three storage cells able to store three bytes, namely, B₁, B₂ and B₃ and a two-bit flip-flop, which can therefore be in any one of four logic states,

a logic comparison circuit incorporating a first group of three byte comparators with two inputs, one input connected to a respective one of the first group of three storage cells and the other input connected to one of the parallel outputs of the three first cells of the shift register, said first group carrying out a first test involving bytes C₁, C₂ and C₃ and bytes A₁, A₂ and A₃, a second group of three byte comparators with two inputs, one input connected to the output of a respective one of the second group of three storage cells and the other to one of the parallel outputs of the three first cells of the shift register, said second group carrying out a second test involving bytes C₁, C₂ and C₃, and finally an article start code detector connected to the parallel outputs of the last two cells of the shift register,

a comparison synthesis logic circuit connected to said first and second groups of comparators, to the start code detector and to the flip-flop, said circuit supplying an opening or closing control signal applied to the control input of the memory, as a function of the result of said tests,

a state of the flip-flop defining a resetting of the storage cells,

the microprocessor loading in an appropriate manner the storage cells with said bytes A1, A2 and A3 defining a page to be selected and with said bytes B1, B2 and B3 defining a threshold, such that all the articles whose classification bytes C1, C2 and C3 exceed this threshold, bring about the appearance of the memory opening signal, said microprocessor checking after each data transmission cycle the state of the memory in order to raise or lower the threshold, or leave it unchanged.