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Data processing apparatus with clock signal control by microinstruction for reduced power consumption and method therefor

  • US 4,615,005 A
  • Filed: 07/20/1984
  • Issued: 09/30/1986
  • Est. Priority Date: 10/27/1980
  • Status: Expired due to Term
First Claim
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1. In a data processing apparatus for carrying out data processing, including data processing means having logic circuits including C-MOS devices, memory means for storing at least one data processing program, clock signal generating means for generating a clock signal to be supplied to said data processing means including said logic circuits, and clock signal supplying means for controlling the supply of said clock signal to said data processing means including said logic circuits, said data processing program including a plurality of data processing instructions, said data processing means operating to successively read out said data processing instructions stored in said memory means to carry out various operations including data processing, said clock signal having a first potential level and a second potential level which is different from said first potential level, said first and second potential levels repeating in turn at a predetermined clock period,a method of controlling the supply of said clock signal to said data processing means including said logic circuits comprising the steps of:

  • storing data processing instructions including at least one clock signal supply inhibit instruction in said memory means prior to carrying out data processing;

    reading out each of said data processing instructions from said memory means;

    decoding and identifying each of said data processing instructions read out of said memory means including said clock signal supply inhibit instruction; and

    generating a clock signal supply stopping signal and supplying said clock signal supply stopping signal to said clock signal supplying means when any one of said data processing instructions is identified as the clock signal supply inhibit instruction to inhibit said clock signal from being supplied from said clock signal generating means to a predetermined part of said data processing means having logic circuits by maintaining the potential level of said clock signal supplied to said predetermined part at said first potential level or said second potential level, whereby power consumption in said logic circuit is reduced.

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