Data processing apparatus with clock signal control by microinstruction for reduced power consumption and method therefor

• US 4,615,005 A
• Filed: 07/20/1984
• Issued: 09/30/1986
• Est. Priority Date: 10/27/1980
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kihara, Toshimasa, Akao, Yasushi, Katsura, Koyo, Maejima, Hideo
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/632,820
• Time in Patent Office: 802 Days
• Field of Search: 364/200, 364/900, 364/707, 307/208
• US Class Current: 713/601
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.

Claims

1. In a data processing apparatus for carrying out data processing, including data processing means having logic circuits including C-MOS devices, memory means for storing at least one data processing program, clock signal generating means for generating a clock signal to be supplied to said data processing means including said logic circuits, and clock signal supplying means for controlling the supply of said clock signal to said data processing means including said logic circuits, said data processing program including a plurality of data processing instructions, said data processing means operating to successively read out said data processing instructions stored in said memory means to carry out various operations including data processing, said clock signal having a first potential level and a second potential level which is different from said first potential level, said first and second potential levels repeating in turn at a predetermined clock period,

a method of controlling the supply of said clock signal to said data processing means including said logic circuits comprising the steps of:

storing data processing instructions including at least one clock signal supply inhibit instruction in said memory means prior to carrying out data processing;

reading out each of said data processing instructions from said memory means;

decoding and identifying each of said data processing instructions read out of said memory means including said clock signal supply inhibit instruction; and

generating a clock signal supply stopping signal and supplying said clock signal supply stopping signal to said clock signal supplying means when any one of said data processing instructions is identified as the clock signal supply inhibit instruction to inhibit said clock signal from being supplied from said clock signal generating means to a predetermined part of said data processing means having logic circuits by maintaining the potential level of said clock signal supplied to said predetermined part at said first potential level or said second potential level, whereby power consumption in said logic circuit is reduced.

2. A method as claimed in claim 1, further comprising the steps of:

categorizing said data processing means including said logic circuits into a plurality of predetermined circuit blocks;

storing in said memory means a plurality of clock signal supply inhibit instructions each of which corresponds to a respective one of said plurality of predetermined circuit blocks prior to carrying out data processing; and

when any one of said data processing instructions read out of said memory means and decoded is identified as a clock signal supply inhibit instruction, inhibiting said clock signal from being supplied to that circuit block corresponding to said one clock signal supply inhibit instruction forming said data processing instruction.

3. A method as claimed in claim 2, wherein a plurality of said clock signal supply inhibit instructions are successively read out to inhibit application of said clock signal to the corresponding ones of said circuit blocks.

4. A method as claimed in claim 2, wherein said data processing apparatus includes a clock signal supply inhibit reference register, and further including

storing in said reference register an identification code for identifying selected ones of said predetermined circuit blocks,

when any one of said clock signal supply inhibit instructions is read out, comparing the corresponding predetermined circuit block with said identification codes registered in said reference register, and

when said corresponding predetermined circuit block is found to have its identification code registered in said reference register, inhibiting the supply of said clock signal to said corresponding predetermined circuit block.

5. A method as claimed in claim 4, wherein the contents of said reference register are updated to provide a change of the selected predetermined circuit blocks for which the supply of said clock signal is to be inhibited, and the supply of said clock signal to said circuit blocks corresponding to the updated contents of said reference register is inhibited upon detection and identification of a corresponding clock signal supply inhibit instruction.

6. A method as claimed in claim 1, wherein said data processing apparatus includes means for generating an interrupt signal requesting interrupt processing by said logic circuit and further comprising releasing the inhibiting of the application of said clock signal to said logic circuit in response to generation of said interrupt signal.

7. A method as claimed in claim 6, further including the step of determining whether or not said interrupt signal is to be accepted on the basis of the logical product of said interrupt signal and selected mask logic of said interrupt signal, and initiating the interrupt processing by said logic circuit when said interrupt signal is to be accepted.

8. A method as claimed in claim 1, wherein a plurality of said clock signals are applied to said logic circuit as separate signals.

9. A method as claimed in claim 8, wherein, when the supply of said plural clock signals is inhibited, the inhibition is effected by maintaining one or more of the plural clock signals at a high potential level, while maintaining the remaining clock signals at a low potential level.

10. A method as claimed in claim 1, further comprising the step of supplying interrupt request signals of input/output control units to said clock signal supply means to remove the inhibition of and restart the supply of said clock signal when at least one of said interrupt request signals is supplied, said interrupt request signals being issued from said input/output control units or the like to request said data processing means to accept interrupt processings requested by said input/output control units.

11. A method as claimed in claim 10, further comprising the steps of:

selecting one of said interrupt request signals supplied to said clock signal supply means;

carrying out, when any one of said interrupt request signals to said clock signal supply means is selected, a corresponding interrupt processing to said selected interrupt request signal,

carrying out, when none of said interrupt request signals is selected, processing of data processing instructions succeeding said clock signal supply inhibit instructions.

12. A method as claimed 1, wherein, when said clock supply inhibit instruction is read out, the clock period of said clock signal is made longer than said predetermined clock period and said clock signal of the longer clock period is continuted to be supplied.

13. In a data processing apparatus including a processor, input/output devices whose operations are processed by said processor when interrupt request signals are issued from said input/output devices, wherein said processor includes a register file, an arithmetic circuit, an address register, an instruction register and a decoder, the improvement comprising:

a clock signal generating circuit for generating clock signals, each of said clock signals having a first potential level and a second potential level which is different from said first potential level, said first and second potential levels repeating in turn at a predetermined clock period, said processor being connected to receive said clock signals from said clock signal generating circuit for carrying out data processing in synchronism with said clock signals;

main memory means for storing instructions including clock signal supply inhibit instructions; and

a clock signal supply control circuit connected to receive said clock signals from said clock signal generating circuit as input signals thereto for supplying said clock signals to said processor, said processor including means for reading said instructions including said clock signal supply inhibit instructions out of said main memory means, said decoder including means for decoding said instructions including said clock signal supply inhibit instructions read out of said memory means and for identifying each of said clock signal supply inhibit instructions to generate a clock signal supply stopping signal, and said clock signal supply control circuit including means for inhibiting said clock signals from being supplied to at least part of said processor in response to said clock signal supply stopping signal by maintaining the potential level of said clock signal supplied to said part of said processor at said first or second potential level when at least one of said instructions is identified as said clock signal supply inhibit instruction, and said clock signal supply control circuit including means for restarting the supply of said clock signal when said interrupt request signals are issued.

14. A data processing apparatus as claimed in claim 13, wherein said clock signal supply control circuit comprises:

a clock control circuit including first flip-flop means connected to said decoder for synchronizing said output of said decoder with one of said clock signals and for outputting synchronized output signals when one of said instructions read out of said memory unit is decoded and identified as the clock signal supply inhibit instruction, and second flip-flop means connected to receive said synchronized output signal of said first flip-flop means as an input signal thereof for outputting signals to be used for controlling the supply of said clock signals in order to inhibit the supply of said clock signals; and

clock gating means for inhibiting the supply of said clock signals to said processor means in response to the output signals of said second flip-flop means of said clock control circuit.

15. A data processing apparatus as claimed in claim 14, wherein said clock signal supply control circuit further comprises:

third flip-flop means for synchronizing said interrupt request signals which are input signals of said third flip-flops with said clock signals and for outputting the synchronized interrupt request signals;

logical sum means connected to receive said synchronized output signals of said third flip-flop means as input signals thereof for detecting that at least one of said interrupt request signals is issued and for outputting a signal in response to such detection;

fourth flip-flop means for setting a timing of restarting of the supply of the clock signals in response to the output signal of said logical sum means and for outputting a signal at said timing, the signal output from said fourth flip-flop means being supplied to said second flip-flop means in order to restart the supply of said clock signals.

16. A data processing apparatus as claimed in claim 15, further comprising means for receiving said synchronized interrupt request signals and for selecting one of said synchronized interrupt request signals as the one which is to be processed in order to carry out data processing on the basis of the selected interrupt request signal.

17. In a data processing apparatus including a logic circuit composed of complementary metal oxide devices, said logic circuit including data processing means having at least a register file, an arithmetic circuit, an address register, an instruction register and a decoder, main memory means for storing programmed instructions to carry out data processing, clock signal generating means for generating a clock signal having a first potential level and a second potential level which is different from said first potential level, said first and second potential levels repeating alternately at a predetermined clock period, and clock signal supply control means for controlling said clock signal so as to supply or not to supply said clock signal to said logic circuit, said data processing apparatus successively reading out said instructions stored in said in main memory to carry out data processing;

a method of controlling the supply of said clock signal to said logic circuit comprising the steps of;

storing in said main memory means a clock signal supply inhibit instruction together with other data processing instructions;

reading out said clock signal supply inhibit instruction and said other data processing instructions in a sequence from said main memory means to carry out data processing;

decoding each of the instructions read out of said main memory means and identifying whether or not each of the instructions is said clock signal supply inhibit instruction;

supplying a clock signal supply inhibit signal to said clock signal supply control means from said data processing means when a decoded instruction is identified as the clock signal supply inhibit instruction;

when said decoded instruction is identified as not being the clock signal supply inhibit instruction, carrying out data processing corresponding to said decoded instruction; and

when said decoded instruction is identified as being said clock signal supply inhibit instruction, inhibiting the supply of said clock signal from said clock signal generating means to said data processing means by means of said clock signal supply control means in response to said inhibit signal until an interrupt processing request signal is supplied to said clock signal supply control means, whereby power consumption in said logic circuit is reduced by inhibiting operation in said logic circuit.

18. A method as claimed in claim 17, wherein said logic circuit further includes a timer and serial input/output means, said logic circuit being divided into regions comprising said data processing means, timer and serial input/output means, and wherein said clock signal supply control means includes a reference register for said divided logic circuit, and wherein said method further includes the steps of:

storing in said reference register an identification code corresponding to one of the regions of the divided logic circuit;

when an instruction read out of said main memory means is identified as the clock signal supply inhibit instruction, reading out said identification code to identify one of the regions of the divided logic circuit; and

inhibiting the supply of said clock signal to the region corresponding to said identification code.

20. A method as claimed in claim 17, further comprising the steps of:

supplying an interrupt signal requesting interrupt processing to said clock signal supply control means, and

when said interrupt processing request signal is accepted by said clock signal supply control means, removing said clock signal supply inhibit signal to restart the supply of said clock signal to said logic circuit.

21. A method as claimed in claim 20, further including the steps of:

determining whether or not said interrupt signal is to be accepted on the basis of a logical product of said interrupt signal and a mask logic which determines whether or not said interrupt signal is to be accepted,

restarting the supply of said clock signal to said logic circuit and initiating the interrupt processing corresponding to said interrupt signal when said interrupt signal is determined to be accepted and is accepted, and

reading out instructions following said clock signal inhibit instruction in said main memory means to carry out the corresponding data processing under control of said following instructions when said interrupt signal is determined not to be accepted.

22. A method as claimed in claim 17, wherein said clock signal supplied from said clock signal supplying means to said logic circuit comprises at least a pair of clock signals having the same clock period but being 180°

out of phase.

23. A method as claimed in claim 17, wherein said clock signal is maintained at said first potential level or second potential level so that the inhibition of said supply of said clock signal is effected.

24. A method as claimed in claim 17, wherein, when said clock supply inhibit instruction is read out, the clock period of said clock signal is made longer than said predetermined clock period and said clock signal of the longer clock period is continued to be supplied.

19. A method as claimed in 18, further including the steps of:

updating said identification code in said reference register in dependence upon the region to which the supply of said clock signal is to be inhibited, and

inhibiting the supply of said clock signal to the region corresponding to the updated identification code when the updated identification code is read out.

25. A data processing apparatus comprising:

a logic circuit composed of complementary metal oxide devices, said logic circuit having data processor means including at least a register file, an arithmetic circuit, an address register, an instruction register and an instruction decoder;

main memory means for storing program instructions to carry out data processing, including a clock signal supply inhibit instruction;

clock signal generating means for generating a clock signal having a first potential level and a second potential level which is different from the first potential level, said said first and second potential levels repeating alternately at a predetermined clock period;

clock signal supply control means for controlling said clock signal so as to supply or not supply said clock signal to said logic circuit; and

said processor means operating in response to said clock signal to successively read out instructions stored in said main memory means to carry out data processing;

wherein said clock signal supply control means comprises;

a clock control circuit connected to receive as input signals thereto both a clock signal supply inhibit signal from said decoder and said clock signal from said clock signal generating means, said clock control circuit including means for synchronizing said clock signal supply inhibit signal with said clock signal, said clock signal supply inhibit signal being produced by said instruction decoder when the content of said instruction register which is read out of said main memory means is decoded and identified by said instruction decoder as said clock signal supply inhibit instruction;

first clock gating means for inhibiting the supply of said clock signal in response to said synchronized clock signal supply inhibit signal;

first flip-flop means for storing an interrupt signal at a predetermined timing;

second clock gating means for synchronizing a received interrupt signal requesting interrupt processing with said clock signal to derive a timing signal for storing the synchronized interrupt signal in said first flip-flop means; and

second flip-flop means for setting the timing for releasing the inhibiting of the supply of said clock signal in response to the output of said first flip-flop means.

26. A data processing apparatus as claimed in claim 25, wherein said clock signal supply control means comprises third flip-flop means for synchronizing said clock signal supply inhibit signal with said clock signal and fourth flip-flop means for inhibiting the supply of said clock signal.

27. A data processing apparatus as claimed in claim 25, wherein said first flip-flop means comprises:

a plurality of first flip-flops each provided correspondingly to a different one of a plurality of interrupt signals requesting interrupt processing so as to accept said plurality of interrupt signals, said plurality of first flip-flops operating to synchronize said plurality of interrupt signals with said clock signal for storing said synchronized interrupt signals; and

logical sum means for outputting a logical sum of each of the output signals of said plurality of first flip-flops.

28. A data processing apparatus as claimed in claim 27, wherein said clock signal supply control means further comprises:

a plurality of second flip-flops for preventing chattering each connected in cascade to a different one of said first flip-flops so as to receive the output signals of said first flip-flops, the outputs of said second flip-flops being supplied to said logical sum means.

29. A data processing apparatus as claimed in claim 28, wherein said clock signal supply control means further comprises mask gate means connected to receive the output signals of said second flip-flops for determining whether or not said interrupt signals are to be accepted and for supplying an output signal to said data processor means when one of said interrupt signals is determined to be accepted so as to carry out the interrupt processing.

30. A data processing apparatus as claimed in claim 25, wherein said logic circuit further includes a timer and serial input/output means, said logic circuit divided into three regions corresponding to said data processor means, said timer and said serial input/output means, respectively, and wherein said clock signal supply control means comprises three clock signal supply control circuits each corresponding to a different one of said three regions, to thereby control the supply of said clock signal to each divided region of said logic circuit individually.

31. A data processing apparatus as claimed in claim 25, wherein said clock signal supply control means further comprises a clock signal frequency divider for generating a second clock signal for a longer period than that of said clock signal instead of said clock signal when said clock signal supply inhibit signal is supplied to said clock signal supply control means to thereby supply said second clock signal of longer period to said logic circuit.

32. A data processing apparatus as claimed in claim 31, wherein said clock signal supply control means further comprises a selector for switching a clock signal between said second clock signal of longer period and said clock signal in response to a switching instruction when an instruction is decoded and identified by said instruction decoder as said switching instruction for switching the period of said clock signal from the longer period to a shorter period.