Nonvolatile dynamic ram circuit
First Claim
1. A memory cell comprisinga first transistor having a first terminal coupled to an input/output line, a second terminal and a control terminal for coupling said first terminal to said second terminal responsive to control signals,a first storage capacitor coupled to said second terminal,a second storage capacitor,a second transistor, having a floating gate, coupled between said first and second capacitors in such manner that said second storage capacitor is coupled to said first storage capacitor depending upon the presence or absence of charge on said floating gate, andsaid memory cell storing information with only said first storage capacitor when said floating gate is charged and said memory cell storing information with both said first storage capacitor and said second storage capacitor when said floating gate is discharged.
1 Assignment
0 Petitions
Accused Products
Abstract
A nonvolatile dynamic RAM capable of operating in a dynamic RAM mode and a second, nonvolatile mode, is disclosed. The nonvolatile dynamic RAM has a memory cell having a transfer transistor for coupling a storage capacitor having a floating gate to a bit line. The memory cell holds information by the storage of charge in the storage capacitor and also holds information by the storage of charge in the floating gate. This data can be stored and retrieved in a volatile mode and in a nonvolatile mode. The nonvolatile dynamic RAM has a plurality of these memory cells connected to a bit line which, in turn, is connected to a sense amplifier for determining the presence or absence of storage charges in the storage capacitor of a selected memory cell in the first mode, and for determining the presence or absence of storage charges in the floating gate of the selected memory cell in the second mode.
-
Citations
17 Claims
-
1. A memory cell comprising
a first transistor having a first terminal coupled to an input/output line, a second terminal and a control terminal for coupling said first terminal to said second terminal responsive to control signals, a first storage capacitor coupled to said second terminal, a second storage capacitor, a second transistor, having a floating gate, coupled between said first and second capacitors in such manner that said second storage capacitor is coupled to said first storage capacitor depending upon the presence or absence of charge on said floating gate, and said memory cell storing information with only said first storage capacitor when said floating gate is charged and said memory cell storing information with both said first storage capacitor and said second storage capacitor when said floating gate is discharged.
-
3. A memory circuit capable of information storage in two modes comprising
a plurality of memory cells, each cell having a storage capacitor formed of a fixed capacitance structure and a variable capacitance structure, said storage capacitor having a floating gate to vary the capacitance of said storage capacitor by isolating the variable capacitance structure from the fixed capacitance structure so as to operate in a low capacitor state or by coupling the variable capacitance structure with the fixed capacitance structure so as to operate in a high capacitor state and a transistor for selectively coupling said storage capacitor to a sense line responsive to a selection signal, said floating gate being charged to define the low capacitor state and being uncharged to define the high capacitor state, said floating layer having a double level construction so that it is closer in proximity to a first region than to a second region, and a sense amplifier connected to said sense line for determining the presence or absence of stored charges in said low capacitor state in a first mode, and for determining the presence or absence of stored charges in said high capacitor state in a second mode.
-
13. A memory cell comprising:
-
a storage capacitor having a fixed capacitance structure and a variable capacitance structure; said storage capacitor being formed of first and second regions disposed in a spaced-apart relationship in a semiconductor substrate, a plate layer disposed over said substrate and above said first and second regions, and a floating gate layer disposed between said first and second regions and intermediate said plate layer and said substrate, said floating gate layer being electrically isolated from said first and second regions and said plate layers; said floating gate layer varying the capacitance of said storage capacitor by isolating the variable capacitance structure from the fixed capacitance structure so as to operate in a low capacitance state or by coupling the variable capacitance structure with the fixed capacitance structure so as to operate in a high capacitance state, said floating gate being charged to define the low capacitance state and being uncharged to define the high capacitance state; said floating layer having a double level construction as that it is closer in proximity to said first region than to said second region; a transistor having a first terminal coupled to said storage capacitor, a second terminal coupled to an input/output line, and a control terminal for coupling said storage capacitor through said input/output line responsive to control signals; and said transistor being formed of third and fourth regions disposed in a spaced-apart relationship in said semiconductor substrate and a transfer gate layer disposed over said substrate and between said third and forth regions, said transfer gate layer being electrically isolated from said third and fourth regions. - View Dependent Claims (14, 15, 16, 17)
-
Specification