High speed data communications system

• US 4,615,040 A
• Filed: 06/14/1984
• Issued: 09/30/1986
• Est. Priority Date: 06/14/1984
• Status: Expired due to Fees

• Current Assignee: Coenco Limited Plaiderie St Peter Port Guernsy Channel Islands Great Britain
• Original Assignee: Coenco Limited
• Inventors: Mojoli, Luigi F., Olivieri, Angelo F.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/620,580
• Time in Patent Office: 838 Days
• Field of Search: 375/38, 375/40, 375/58, 375/60, 375/100, 375/103, 375/106, 375/111, 455/59, 455/61, 455/52, 455/133, 455/134, 455/135, 455/65, 455/307, 455/312, 371/36, 371/68, 340/825.01, 364/718, 364/726, 364/825, 328/14, 370/100
• US Class Current: 375/267
• CPC Class Codes: H04L 1/06 using space diversity
• CPC Class Codes: H04L 27/2602 Signal structure

Abstract

An improved data transmission system has a transmitter which includes a modulator responsive to a synthesized modulating signal, which provides for transmission of data substreams on parallel subchannels, for example, by using subcarrier frequencies. At the receiver the subcarriers are received and data is selected from the received subcarriers at two diverse receivers. In addition, there are provided signals added to the transmitted data for retiming the data at the receiver.

Claims

1. A system for transmission and reception of a serial stream of digital data from a first location to a second location comprising:

means at said first location for converting said serial data stream into a number N of first parallel data substreams;

a number N of modulators at said first location for modulating a plurality of component signals each with one of said parallel data substreams;

means for transmitting said modulated component signals to said second location, each of said component signals being transmitted on at least two transmission channels;

a plurality of at least 2N demodulators at said second location, each for demodulating a component signal from one of said transmission channels;

switching means at said second location for selecting the output of one of said demodulators for each of said modulated component signals, to derive a number N of second parallel data substreams, each corresponding to one of said first data substreams;

means for converting said N second parallel data substreams into an output serial data stream.

2. A system as specified in claim 1 wherein said modulators modulate a plurality of component signals, each having a selected frequency within a frequency band.

3. A system as specified in claim 1 wherein said means for transmitting said modulated component signals to said second location comprises means for transmitting a composite signal derived from said component signals.

4. A system as specified in claim 3 wherein said modulators modulates a plurality of component signals, each comprising different frequency within a selected frequency band, and wherein said transmitting means transmits a composite signal comprising said component signals as subcarriers.

5. A system as specified in claim 1 wherein said transmission channels comprise channels having different transmission paths in space.

6. A system as specified in claim 1 wherein said transmission channels comprise transmissions at different frequency bands.

7. A system as specified in claim 1 wherein said transmission channels comprise transmissions with different polarities.

8. A system as specified in claim 1 wherein there are further provided means at said second location for generating signals representative of the amplitude of each of said component signals from each of said transmission channels, and wherein said switching means is responsive to said amplitude representative signals.

9. A system as specified in claim 1 wherein there are further provided means at said second location for generating signals representative of the bit error rate for each of said component signals from each of said transmission channels, and wherein said switching means is responsive to said bit error rate representative signals.

10. A receiver for use in a system having at least two different transmission channels for receiving a plurality of N component signals, each of which is transmitted on at least two of said channels, said component signals having modulation corresponding to N parallel data substreams, comprising:

at least N first demodulators, each coupled to receive one of said component signals from one of said channels and to provide at least N first output data substreams;

at least N second demodulators, each coupled to receive one of said component signals from another of said channels and to provide at least N second output data substreams; and

switching means for selecting one of said first or second output data substreams for each of said N parallel data substreams in accordance with the component signals for each of said N parallel data substreams on each of said transmission channels.

11. A receiver as specified in claim 10 further including means for generating signals representative of the amplitude of each of said component signals on each of said channels, and wherein said switching means is responsive to said amplitude representative signals.

12. A receiver as specified in claim 10 further including means associated with each of said first and second demodulators for generating signals representative of the bit error rate for each of said first and second output data substreams, and wherein said switching means is responsive to said bit error rate representative signals.

13. A system for transmission and reception of a serial stream of digital data from a first location to a second location, comprising:

means at said first location, responsive to said serial data stream, for forming a plurality of N parallel data substreams, each of said substreams comprising a series of data frames, each of said data frames including a data frame timing signal and a predetermined quantity of digital data;

N modulators at said first location, each for modulating a component signal with one of said N data substreams;

means for transmitting said modulated component signals to said second location;

N demodulators at said second location for demodulating said modulated component signals to derive therefrom said N parallel data substreams;

means responsive to said frame timing signals in said demodulated data substreams for retiming said digital data in said substreams; and

means responsive to said retimed substream digital data for generating an output serial stream of digital data.

14. A system as specified in claim 13 wherein said means for forming said data substreams forms said substreams with frame timing signals comprising a selected sequence of digital bits, said sequence being the same for all frames in a substream.

15. A system as specified in claim 14 wherein said retiming means includes a comparator for comparing the digital bits in each of said substreams to said selected sequence.

16. A system as specified in claim 15 wherein said retiming means includes means responsive to said timing signals in sequential data frames.

17. A system as specified in claim 13 wherein said retiming means includes a first-in-first-out memory for digital data having separate data-in and data-out clock inputs.

18. A system as specified in claim 17 wherein said memory has a first memory channel for data signals, a second memory channel for signals derived from said frame timing signals, and a third memory channel for service channel.

19. In a system for transmission of a stream of digital data between remote locations, said system having signal filtering characteristics, signal forming apparatus, comprising:

a register for storing digital data bits in said data stream in an arrangement corresponding to the order of said bits in said stream;

a counter, responsive to supplied clock signals;

a programmed digital data memory having first address inputs coupled to said register and second address inputs coupled to said counter and having programmed data values corresponding to sequential values of a synthesized modulating signal, said data values being selected to provide a synthesized modulating signal with a Fourier Transform dependent on said data bits in said register which compensate for said signal filtering characteristics; and

a digital to analog converter responsive to data values from said memory.

20. Signal forming apparatus as specified in claim 19 wherein said data stream comprises digital data bits at a bit-clock rate and wherein said register comprises a shift register clocked at said bit clock rate.

21. Signal forming apparatus as specified in claim 20 wherein said counter is an M-bit digital counter, and wherein said supplied clock signals occur at a rate which is 2^M times said bit-clock rate.

22. Signal forming apparatus as specified in claim 19 wherein said signal filtering characteristics include spectral amplitude and group delay characteristics, and wherein said memory has data values selected to compensate for said spectral amplitude and group delay characteristics.

23. In a system for transmitting a stream of digital data between remote locations, said system having signal filtering characteristics, a modulator for modulating a supplied carrier with said data, comprising:

a register for storing digital data bits in said data stream in an arrangement corresponding to the order of said bits in said stream;

a counter, responsive to supplied clock signals;

a programmed digital data memory having first address inputs coupled to said register and second address inputs coupled to said counter and having programmed data values corresponding to sequential values of a synthesized modulating signal, said data values being selected to provide a synthesized modulating signal with a Fourier Transform dependent on said data bits in said register which compensate for said signal filtering characteristics;

a digital to analog converter responsive to data values from said memory for generating a modulating signal; and

a modulator for modulating said carrier with said modulating signal.

24. Modulating apparatus as specified in claim 23 wherein said data stream comprises digital data bits supplied at a bit-clock rate and wherein said register comprises a shift register clocked at said bit clock rate.

25. Modulating apparatus as specified in claim 24 wherein said counter is an M-bit digital counter, and wherein said supplied clock signals occur at a rate which is 2^M times said bit-clock rate.

26. Modulating apparatus as specified in claim 23 wherein said signal filtering characteristics include spectral amplitude and group delay characteristics, and wherein said memory has data values selected to compensate for said spectral amplitude and group delay characteristics.

27. A system for transmission and reception of a serial stream of digital data from a first location to a second location and having signal filtering characteristics, comprising:

(1) means at said first location responsive to said serial data stream, for forming a plurality of N parallel data substreams, each of said substreams comprising a series of data frames, each of said data frames including a data frame timing signal and a predetermined quantity of digital data;

(2) at least N modulators, each comprising;

(a) a register for storing digital data bits in one of said substreams in an arrangement corresponding to the order of said bits in said substream;

(b) a counter, responsive to supplied clock signals;

(c) a programmed digital data memory having first address inputs coupled to said register and second address inputs coupled to said counter and having programmed data values corresponding to sequential values of a synthesized modulating signal, said data values being selected to provide a synthesized modulating signal with a Fourier Transform dependent on said data bits in said register which compensate for said signal filtering characteristics;

(d) a digital to analog converter responsive to data values from said memory; and

(e) means for modulating a supplied component signal with said synthesized modulating signal;

(3) means for transmitting said modulated component signals to said second location;

(4) N demodulators at said second location for demodulating said modulated component signals to derive therefrom said N parallel data substreams;

(5) means responsive to said frame timing signals in said demodulated data substreams for retiming said digital data in said substreams; and

(6) means responsive to said retimed substream digital data for generating an output serial stream of digital data.

28. A system as specified in claim 27 wherein said means for forming said data substreams forms said substreams with frame timing signals comprising a selected sequence of digital bits, said sequence being the same for all frames in a substream.

29. A system as specified in claim 28 wherein said retiming means includes a comparator for comparing the digital bits in each of said substreams to said selected sequence.

30. A system as specified in claim 29 wherein said retiming means includes means responsive to said timing signals in sequential data frames.

31. A system as specified in claim 27 wherein said retiming means includes a first-in first-out memory for digital data having separate data-in and data-out clock inputs.

32. A system as specified in claim 31 wherein said memory has a first memory channel for data signals and a second memory channel for signals derived from said frame timing signals.

33. A system as specified in claim 27 wherein each of said data substreams comprises digital data bits at a bit-clock rate and wherein each of said registers comprises a shift register clocked at said bit clock rate.

34. A system as specified in claim 33 wherein each of said counters is an M-bit digital counter, and wherein said supplied clock signals occur at a rate which is 2^M times said bit-clock rate.

35. A system as specified in claim 27 wherein said signal filtering characteristics include spectral amplitude and group delay characteristics, and wherein each of said memories has data values selected to compensate for said spectral amplitude and group delay characteristics.