Frame addressed spatial light modulator

• US 4,615,595 A
• Filed: 10/10/1984
• Issued: 10/07/1986
• Est. Priority Date: 10/10/1984
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hornbeck, Larry J.
• Primary Examiner(s): HAROIAN, HARRY
• Application Number:
  US06/659,387
• Time in Patent Office: 727 Days
• Field of Search: 353/122, 353/120, 350/356, 350/359-361, 350/266, 350/269, 340/815.04, 358/231
• US Class Current: 353/122
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means
• CPC Class Codes: H01L 27/14818 Optical shielding
• CPC Class Codes: H01L 27/1485 Frame transfer

Abstract

A frame addressed spatial light modulator with pixels arranged along columns of charge transfer devices, and optical projection and processing systems using such modulators are disclosed. The pixels include electrostatically deflectable flaps supported by conducting posts with nodes gated to the charge transfer device. Schlieren, dark field and reverse dark field optics are available.

Claims

1. A frame addressed spatial light modulator, comprising:

(a) a two dimensional array of pixels on a substrate and arranged into columns, each of said pixels including (i) a column transfer portion, (ii) a sense portion adjacent said column transfer portion, (iii) a conducting layer over at least a part of said portion, and (iv) at least one deflectable reflecting flap connected to said sense portion and over but insulated from said layer;

(b) a column transfer gate for transferring signals from the column transfer portion of a pixel to the column transfer portion of an adjacent pixel in the same column; and

(c) a sense transfer gate for transferring signals from the column transfer portion of a pixel to the sense portion of the same pixel.

2. The modulator of claim 1, wherein:

(a) said column transfer portions of the pixels in one of said columns together form a CCD.

3. The modulator of claim 2, wherein:

(a) said CCD is a buried channel, virtual phase CCD; and

(b) said column transfer gate is the clocked gate for said buried channel, virtual phase CCD.

4. The modulator of claim 1, wherein:

(a) said sense portion includes (i) a node region to which said flap is connected and (ii) a potential well region adjacent said node region; and

(b) said sense transfer gate directly controls the potential in said potential well region but not in said node region.

5. The modulator of claim 4, further comprising:

(a) circuitry for applying preset voltage pulses to said sense transfer gate and pumping charge from said node region by repeatedly lowering the potential in said potential well region to withdraw charge from said node region to recombine with trapped charge of opposite sign followed by raising the potential to recharge said trapped charge.

6. The modulator of claim 1, further comprising:

(a) circuitry for biasing said conducting layer with respect to said substrate.

7. A frame addressed spatial light modulator, comprising:

(a) a plurality of parallel CCDs on a substrate;

(b) a plurality of sense nodes on said substrate, each of said nodes adjacent one of said CCDs;

(c) at least one frame transfer gate for transferring change packets from potential wells in said CCDs to said nodes; and

(d) a plurality of electrostatically deflectable reflecting flaps conductively supported by flap supports on said nodes, each of said nodes connected to at least one of said flap supports.

8. The modulator of claim 7, further comprising:

p1 (a) at least one ground plane between at least one of said flaps and said substrate including said CCDs and said transfer gate(s), said ground plane(s) insulated from said flaps, supports, and nodes.

9. The modulator of claim 7, wherein:

(a) said CCDs are buried channel, virtual phase CCDs.

10. The modulator of claim 7, wherein:

(a) said frame transfer gates may be biased sufficiently to pump essentially all of a charge packet from said nodes, supports and flaps into said substrate and thereby preset said nodes, supports, and flaps for another frame of charge packets.

11. The modulator of claim 8, wherein:

(a) said ground planes are insulated from said substrate, CCDs, and transfer gates and may be biased with respect to said substrate.

12. A frame addressed spatial light modulator, comprising:

(a) an array of pixels on a substrate and arranged into columns;

(b) charge transfer devices on said substrate for transferring signal charge packets down said columns;

(c) a serial to parallel converter on said substrate, the outputs of said converter connected to said charge transfer devices;

(d) frame transfer gates on said substrate for transferring signal charge packets from said columns to said pixels essentially simultaneously for all pixels; and

(e) said pixels characterized by a sense node on said substrate connected to at least one electrostatically deflectable, reflecting flap supported on said substrate.

13. The modulator of claim 12, further comprising:

(a) at least one ground plane, each of said ground planes(s) between at least one of said flaps and said substrate including said transfer gates and charge transfer devices and each of said ground plane(s) insulated to be biased (positive, negative, or zero) with respect to said substrate.

14. The modulator of claim 12, further comprising:

(a) circuitry for applying preset voltage pulses to said frame transfer gate and pumping charge from said sense node by repeatedly lowering the potential in a portion of said pixel adjacent said node to withdraw charge from said node to recombine with trapped charge of opposite sign followed by raising the potential to recharge said trapped charge.

15. An image projection system for electronic image data, comprising:

(a) a light source;

(b) a spatial light modulator of said data;

(c) an optical system for directing light from said source onto said modulator and for projecting modulated light from said modulator onto a projection screen; and

(d) said modulator including;

(i) a plurality of parallel CCDs on a substrate;

(ii) a plurality of sense nodes on said substrate, each of said nodes adjacent one of said CCDs;

(iii) at least one frame transfer gate for transferring charge packets from potential wells in said CCDs to said nodes;

(iv) a plurality of electrostatically deflectable reflecting flaps conductively supported by flap supports on said nodes, each of said nodes connected to at least one of said flap supports; and

(v) a converter for inputting said data into said CCDs.

16. The system of claim 15, further comprising:

(a) circuitry for applying preset voltage pulses to said frame transfer gate(s) and pumping charge from each of said nodes by for each node repeatedly lowering the potential in a region adjacent to said each node to withdraw charge from said each node to recombine with trapped charge of opposite sign followed by raising the potential to recharge said trapped charge.

17. An optical processor for electronic data, comprising:

(a) a light source;

(b) a spatial light modulator for said data;

(c) an optical system for directing light from said source onto said modulator and for converting modulated light from said modulator into electronic output; and

(d) said modulator including;

(i) a plurality of parallel CCDs on a substrate;

(ii) a plurality of sense nodes on said substrate, each of said nodes adjacent one of said CCDs;

(iii) at least one frame transfer gate for transferring charge packets from potential weels in said CCDs to said nodes;

(iv) a plurality of electrostatically deflectable reflecting flaps conductively supported by flap supports on said nodes, each of said nodes connected to at least one of said flap supports; and

(v) a converter for inputting said data into said CCDs.

18. The processor of claim 17, further comprising:

(a) circuitry for applying preset voltage pulses on said frame transfer gate(s) and pumping charge from each of said nodes by for each node repeatedly lowering the potential in a region adjacent to said each node to withdraw charge from said each node to recombine with trapped charge of opposite sign followed by raising the potential to recharge said trapped charge.