Data processing system

• US 4,616,311 A
• Filed: 04/29/1985
• Issued: 10/07/1986
• Est. Priority Date: 10/03/1980
• Status: Expired due to Fees

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Sato, Fumitaka
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/727,197
• Time in Patent Office: 526 Days
• Field of Search: 369/200 MS File, 369/900 MS File
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

A data processing system having an address conversion system for translating a virtual address into a real address, including a main memory for storing instructions and data and a second memory for storing an address conversion table including a plurality of entries, each of which consists of a plurality of control bits and a portion of a real address. A central processing unit executes the instruction stored in the main memory according to a microprogram. An addressing means addresses the second memory by a continuous portion, which includes the effective upper most bit of the virtual address for the address conversion and for updating of the conversion table. The main memory need not store the conversion table.

Claims

1. A virtual memory data processing system comprising:

main memory means for storing instructions and data;

second memory means for storing an entire address conversion table comprising a plurality of entries each of which includes a plurality of control bits and a portion of a real address corresponding to a continuous portion of the bits which form a virtual address and to each of which an address defined by said continuous portion of the corresponding virtual address is assigned;

instruction execution means for executing said instructions in said main memory means and supplying said second memory means with a virtual address to access said main memory means;

second memory addressing means for addressing said second memory means by said continuous portion of said virtual address supplied by said instruction execution means both for the purpose of address conversion and for the purpose of updating the address conversion table, said continuous portion including the effective most upper bit of said virtual address;

main memory addressing means for concatenating said portion of a real address delivered from said second memory means for address conversion and the remaining part of said virtual address supplied by said instruction execution means so that said instruction execution means access said main memory;

said instructions including at least one instruction for handling contents of said entry in said second memory means; and

said instruction execution means revising the contents of said second memory means only when said at least one second memory handling instruction is executed and referencing the contents of said second memory means only for the purpose of address conversion when an instruction other than said at least one second memory handling instruction is executed.

2. A virtual memory data processing system as recited in claim 1, wherein said at least one instruction comprises:

an operation code part for defining an instruction as said second memory handling instruction,

a part for designating a virtual address, and

an auxiliary operation designating part for designating a plurality of operations including an operation for setting the contents of said entry and an operation for handling said control bits of said entry.

3. A virtual memory data processing system as recited in claim 2, further comprising:

register means for storing address information for accessing an entry of said second memory means;

said part of said second memory handling instruction for designating a virtual address designating a said register means; and

address information stored in said register means designated by said part being supplied to said second memory addressing means when said instruction execution means executes the second memory handling instruction.