Microcomputer controlled data receiver

• US 4,616,314 A
• Filed: 05/12/1983
• Issued: 10/07/1986
• Est. Priority Date: 05/12/1983
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Edwards, Shannon, Wilson, James L.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/493,919
• Time in Patent Office: 1,244 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 455/62, 455/54, 455/137, 371/37, 371/40
• US Class Current: 710/267
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes
• CPC Class Codes: H04L 5/04 the signals being represented by different amplitudes or polarities, e.g. quadriplex

Abstract

A data receiver is described that includes a microcomputer that is coupled to a self-clocking asynchronous data bus. The data bus includes three signal lines TDATA, CDATA and RDATA. Bits of a data block are detected by a first exclusive-OR gate that is coupled to the TDATA and CDATA lines. An interrupt control signal and the output of the first exclusive-OR gate are coupled to a second exclusive-OR gate that generates an interrupt signal. The interrupt signal is coupled to the interrupt input of the receiving microcomputer. The receiving microcomputer is interrupted in response to a data bit and then changes the binary state of the interrupt control signal for producing an interrupt for the idle state between data bits. Upon being interrupted by the idle state between data bits, the receiving microcomputer changes the binary state of the interrupt control signal for producing an interrupt for the next data bit and also applies a bit of return data to the RDATA line. The received data block may include an address and a data portion.

Claims

1. A method for enabling processing means to receive a block of binary data bits from first and second data signals generated by a signal source, the first and second data signals having a binary zero state before and after the block of data bits, the first data signal having the binary zero state and the second data signal having a binary one state for data bits having a binary zero state, the first data signal having a binary one state and the second data signal having the binary zero state for data bits having a binary one state, and the first and second data signals having the binary one state between successive data bits, said processing means generating a binary interrupt control signal initially having a binary one state, said method comprising for each data bit the steps of:

(a) generating data transition signal having a binary one state when the first and second data signals have different states and having a binary zero state when the first and second data signals have the same state;

(b) interrupting the processing means when the data transition signal and the interrupt control signal have the same state;

(c) storing the data bit in the processing means in response to said interrupting step, the first data signal and a binary one state of the interrupt control signal; and

(d) changing the state of the interrupt control signal in response to the binary one state of the interrupt control signal.

2. The method according to claim 1, wherein the block of data bits includes an address portion having a first predetermined number of bits followed by a data portion having a second predetermined number of bits, said storing step (c) further including the steps of:

counting the number of times said processing means is interrupted by said interrupting step (b);

storing each of the data bits in an address register until the counted number of interrupts is substantially the same as the first predetermined number; and

storing each of the following data bits in a data register until the counted number of interrupts is substantially the same as the sum of the first predetermined number and the second predetermined number.

3. The method according to claim 1, wherein said storing step (c) stores the data bit in response to said interrupting step, the first and second data signals and a binary one state of the interrupt control signal.

4. Apparatus for enabling processing means to receive a block of binary data bits from first and second data signals generated by a signal source, the first and second data signals having a binary zero state before and after the block of data bits, the first data signal having the binary zero state and the second data signal having a binary one state for data bits having a binary zero state, the first data signal having a binary one state and the second data signal having the binary zero state for data bits having a binary one state, and the first and second data signals having the binary one state between successive data bits, said apparatus comprising:

means coupled to the first and second data signals for generating a data transition signal having a binary one state when the first and second data signals have different states and having a binary zero state when the first and second data signals have the same state;

means coupled to the data transition signal generating means for generating an interrupt signal having a binary one state when the data transition signal and an interrupt control signal have the same binary state and otherwise having a binary zero state; and

processing means coupled to the interrupt signal generating means for producing the interrupt control signal initially having a binary one state, said processing means being responsive to the binary one state of the interrupt signal for storing a data bit when the interrupt control signal has the binary one state, and said processing means further being responsive to the binary one state of the interrupt signal for changing the binary state of the interrupt control signal.

5. The apparatus according to claim 4, wherein the data transition signal generating means is comprised of exclusive-OR gating means.

6. The apparatus according to claim 4, wherein the interrupt signal generating means is comprised of exclusive-OR gating means.

7. The apparatus according to claim 4, wherein the block of data bits includes an address portion having a first predetermined number of bits and a data portion having a second predetermined number of bits, and wherein said processing means further includes an address register, a bit counter and a data register, said processing means incrementing the bit counter by one in response to the binary one state of the interrupt signal, storing each of the data bits in the address register until the bit counter is substantially the same as the first predetermined number, and thereafter storing each of the data bits in the data register until the bit counter is substantially the same as the sum of the first predetermined number and the second predetermined number.

8. The apparatus according to claim 7, wherein said processing means includes a transmit data register having bits of a transmit data signal therein and a return data signal coupled to said transmit data register, said processing means shifting data bits in the transmit data register by one bit in response to the binary one state of the interrupt signal and the binary zero state of the interrupt control signal.