CMOS backup power switching circuit

• US 4,617,473 A
• Filed: 01/03/1984
• Issued: 10/14/1986
• Est. Priority Date: 01/03/1984
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Intersil Inc (Renesas Electronics Corporation)
• Inventors: Bingham, David
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Jennings, Derek S.
• Application Number:
  US06/567,577
• Time in Patent Office: 1,015 Days
• Field of Search: 307/64, 307/66, 307/584, 307/87, 307/44, 307/80, 307/46, 307/81, 307/48, 307/362, 365/229, 323/244, 323/283, 323/284, 323/299
• US Class Current: 307/66
• CPC Class Codes: H02J 9/061 for DC powered loads

Abstract

A load circuit is provided with a backup power supply to power the essential functions of the load in the event that its primary power supply fails or is otherwise degraded. The positive terminals of both the primary power supply and the backup power supply, having a common negative reference, are input to a differential voltage comparator circuit. The output of the differential voltage comparator circuit controls a switching transistor located in a line between the primary power supply and the load, and when inverted by an inverter circuit, controls a second switching transistor located in a line between the backup power supply and the load. In operation, only the more positive of the primary power or the backup power supply voltages is provided to the load. The output of the inverter circuit is also available to indicate which of the two sources the power is applied to the load, and may be further used to disable non-essential portions of the load circuitry.

Claims

1. A backup power switching circuit comprising:

at least first, second, third, fourth, fifth, and sixth p-channel MOS transistors, each of said transistors including a control electrode, an output electrode, an input electrode; and

a substrate;

at least first, second, third, fourth, and fifth n-channel MOS transistors, each of said transistors including a control electrode, an output electrode, an input electrode, and a substrate;

a high resistive impedance;

a reference terminal, adapted to provide a reference potential;

a first input terminal, coupled to the input electrode of said first p-channel MOS transistor, and to the control electrode of said first n-channel MOS transistor;

a second input terminal, coupled to the input electrode of said second p-channel MOS transistor, and to the control electrode of said second n-channel MOS transistor;

an output terminal, coupled to the output electrodes of said first and second p-channel MOS transistors;

means for applying a first direct current potential to said first input terminal;

means for applying a second direct current potential to said second input terminal, said second direct current potential having the same polarity relative to said reference terminal as said first direct current potential; and

coupling means for coupling said transistors and said terminals wherein;

(a) the control electrode of said first p-channel MOS transistor is coupled to the output electrode of said fifth p-channel MOS transistor and to the input electrode of said fourth n-channel MOS transistor, and the control electrode of said second p-channel MOS transistor is coupled to the output electrode of said sixth p-channel MOS transistor and to the input electrode of said fifth n-channel MOS transistor;

(b) said first and second n-channel MOS transistors have their substrates coupled together and to said reference terminal, providing a reverse bias with respect to their respective input electrodes, and their output electrodes are together coupled through said high resistive impedance to the input electrode of said third n-channel MOS transistor and to the control electrodes of said third and fourth n-channel MOS transistors;

(c) the output electrodes of said third and fourth n-channel MOS transistors are jointly coupled to said reference terminal and to the output electrode of said fifth n-channel MOS transistor;

(d) the input electrode of said first n-channel MOS transistor is coupled to the output electrode of said third p-channel MOS transistor and to the control electrodes of said third and fourth p-channel MOS transistors;

(e) the input electrode of second second n-channel MOS transistor is coupled to the output electrode of said fourth p-channel MOS transistor and to the control electrode of said fifth p-channel MOS transistor;

(f) the input electrodes of said third and fourth p-channel MOS transistors are coupled to the output electrode of said first p-channel MOS transistor, to said output terminal, and to the input electrodes of said fifth and sixth p-channel MOS transistors; and

(g) the output electrode of said fifth p-channel MOS transistor and the input of electrode of said fourth n-channel MOS transistor are further coupled to the control electrodes of said sixth p-channel MOS transistor and said fifth n-channel MOS transistor;

wherein, in dependence on the relative magnitudes of the direct current potentials applied to said first and second input terminals, said first or said second p-channel MOS transistor is driven into conduction to couple said input terminal having the greater magnitude to said output terminal.

2. A backup power switching circuit as in claim 1, wherein said output electrode of said sixth p-channel MOS transistor and said input electrode of said fifth n-channel MOS transistor are jointly further coupled to an indicator output terminal.

3. A backup power switching circuit as in claim 1 wherein said transistors, said high resistive impedance;

and said coupling means comprise an integrated microcircuit.

4. A backup power switching circuit comprising:

first and second transistors, each of said transistors including a control electrode, an output electrode, an input electrode, and a substrate;

a reference terminal, adapted to provide a reference potential;

a differential voltage comparator including an inverting input, a non-inverting input, and an output coupled to the control input of said first transistor;

a voltage inverter having an input coupled to the output of the comparator, and an output coupled to the control input of the second transistor;

a first input terminal, coupled to the input electrode of said first transistor and to the inverting input of said comparator;

a second input terminal, coupled to the input electrode of said second transistor and to the non-inverting input of said comparator; and

an output terminal coupled to the output electrodes of said first and second transistors;

wherein, in dependence on the relative magnitudes of the potentials applied to said first and second input terminals, said first or second transistor is driven into conduction to couple the input terminal having the greater magnitude to said output terminal.

5. A backup power switching circuit as in claim 4 wherein parasitic diodes are formed between said output electrodes and said substrates of said transistors, thereby providing alternate current paths of low impedance.