Programmable logic array device using EPROM technology

• US 4,617,479 A
• Filed: 05/03/1984
• Issued: 10/14/1986
• Est. Priority Date: 05/03/1984
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chan, Yiu-Fai, Wong, Sau-Ching, Hartmann, Robert F., Ou, Jung-Hsing
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/607,018
• Time in Patent Office: 894 Days
• Field of Search: 307/465, 307/468, 307/469, 307/473, 307/475, 340/825.83, 364/716, 364/900 MS File, 365/94, 365/103, 365/104, 365/184, 365/185
• US Class Current: 365/185.17
• CPC Class Codes: H03K 19/09425 Multistate logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/17712 one of the matrices at least being reprogrammable
• CPC Class Codes: H03K 5/023 using field effect transistors

Abstract

The programmable logic array device basically comprises a programmable AND array (FIGS. 5, 11) having a plurality of memory cells (30, 31) arranged in addressable rows (40-45) and columns (32-38) and which can be individually programmed to contain logic data; an input circuit (FIG. 9) for receiving an input signal and for developing a buffered signal corresponding thereto; a first row driver (FIG. 10) responsive to the buffered signal and operative to interrogate a particular row of the memory cells and to cause the AND array to output signals corresponding to the data contained therein; first sensing circuitry (FIG. 12) for sensing the signals output by the AND array and for developing corresponding data signals which are the logical OR of signals output by the AND array; first output terminal circuitry; and first switching circuitry (FIG. 14) responsive to a control signal and operative to couple the data signal either into the storage circuitry or to the output terminal circuitry (FIG. 16). The device has the advantages generally of greater logic density and lower system power than standard family logic components.

Claims

1. A programmable logic array device comprising:

means forming a first programmable AND array having a plurality of memory cells arranged in addressable rows and columns and which can be individually programmed to contain logic data;

first input circuit means for receiving a first input signal and for developing a first buffered signal corresponding thereto;

first row driver means responsive to said first bufferred signal and operative to interrogate a particular row of said memory cells and to cause said first AND array to output signals corresponding to the data contained therein;

first sensing means for sensing the signals output by said first AND array and for developing a corresponding first data signal which is the logicial OR of the signals output by said first AND array;

first signal storage means for receiving and temporily storing said first data signal;

first output terminal means; and

first switching means responsive to a control signal and operative to couple either said first data signal or a data signal temporarily stored in said first signal storage means to said first output terminal means.

2. A programmable logic array device as recited in claim 1 and further comprising second row driver means responsive to a signal input thereto and operative to interrogate another particular row of said memory cells and to cause said first AND array to output other data signals corresponding to the data contained therein to said first sensing means for developing another data signal.

3. A programmable logic array device as recited in claim 2 wherein said memory cells are formed using EPROM technology.

4. A programmable logic array device as recited in claim 2 wherein said memory cells are formed using EEPROM technology.

5. A programmable logic array device as recited in claim 2 wherein said first switching means is also operative to couple either the data signal output by said first sensing means or a data signal temporarily stored in said first signal storage means into said second row driver means.

6. A programmable logic array device as recited in claim 5 wherein said first switching means includes an output multiplexing device for connecting either the output of said first sensing means or the temporarily stored first data signal contained in said first storage means to said first output terminal means.

7. A programmable logic array device as recited in claim 6 wherein said first switching means further includes a feedback multiplexing circuit operative to couple either the output of said first sensing means, the temporarily stored first data signal, or the data appearing at said first output terminal means to said second row driver means.

8. A programmable logic array device as recited in claim 7 wherein said input circuit means includes a level shifting inverter circuit comprising:

means forming an input terminal for receiving a voltage signal having first and second states;

a level shifting inverter stage including,

a first switching element coupled between a voltage source and a first circuit node, said first switching element being responsive to said voltage signal and operative to switch between a conducting state when said voltage signal is in said first state and a non-conducting state when said voltage signal is in said second state,

a resistive impedence means coupling said first switching element to said voltage source,

a capacitive impedance means coupled between the junction of said resistive impedance means and said first switching element and circuit ground,

a second switching element coupled between said first circuit node and circuit ground, said second switching element being responsive to said voltage signal and operative to switch between a non-conducting state when said voltage signal is in said first state and a conducting state when said voltage signal is in said second state;

means forming an inverter circuit output terminal; and

buffer means coupling said first circuit node to said inverter circuit output terminal wherein said resistive impedance means assists in the switching of said first switching element from said conducting state to said non-conducting state, and wherein said capacitive impedance means serves to improve the switching speed of said first switching element as it switches from said non-conducting state to said conducting state.

9. A programmable logic array device as recited in claim 8 wherein said first row driver means includes a tri-state driver circuit comprising:

means forming a circuit input terminal for receiving said buffered signal, and a circuit output terminal;

a first field effect transistor means responsive to a buffered signal of a first signal state applied to said circuit input terminal and operative to couple said circuit output terminal to a source of potential of a first voltage, said first transistor means having its well region normally connected to said first source of potential;

a second field effect transistor means responsive to a buffered signal of a second signal state applied to said circuit input terminal and operative to couple said circuit output terminal to circuit ground;

gating means responsive to operating mode signals and operative to selectively disable said first and second transistor means; and

a switching device responsive to a first control signal and operative to couple said well region of said first transistor means to a second source of potential of a second voltage substantially greater in magnitude than said first voltage whereby said circuit output terminal may be driven by another signal source to a signal level greater than said first voltage.

10. A programmable logic array device as recited in claim 2 and further comprising additional row driver means responsive to aditional signals input thereto and operative to interrogate other particular rows of said memory cells and to cause said first AND array to output other data signals corresponding to the data contained therein to said first sensing means.

11. A programmable logic array device as recited in claim 1 wherein said input circuit means includes a level shifting inverter circuit comprising:

means forming an input terminal for receiving a voltage signal having first and second states;

a level shifting inverter stage including,

a first switching element coupled between a voltage source and a first circuit node, said first switching element being responsive to said voltage signal and operative to switch between a conducting state when said voltage signal is in said first state and a non-conducting state when said voltage signal is in said second state,

a resistive impedance means coupling said first switching element to said voltage source,

a capacitive impedance means coupled between the junction of said resistive impedance means and said first switching element and circuit ground,

a second switching element coupled between said first circuit node and circuit ground, said second switching element being responsive to said voltage signal and operative to switch between a non-conducting state when said voltage signal is in said first state and a conducting state when said voltage signal is in said second state;

means forming an inverter circuit output terminal; and

buffer means coupling said first circuit node to said inverter circuit output terminal wherein said resistive impedance means assists in the switching of said first switching element from said conducting state to said non-conducting state, and wherein said capacitive impedance means serves to improve the switching speed of said first switching element as it switches from said non-conducting state to said conducting state.

12. A programmable logic array device as recited in claim 11 wherein said first switching element is a P-channel field effect transistor and said second switching element is an N-channel field effect transistor.

13. A programmable logic array device as recited in claim 12 wherein said buffer means includes a second inverter stage coupling said first circuit node to a second circuit node.

14. A programmable logic array device as recited in claim 13 wherein said second inverter stage includes a third switching elements responsive to the voltage level on said first node and operative to either couple said second node to or to decouple said second node from said voltage source, and a fourth switching element responsive to the voltage level on said first node and operative to either decouple said second node from or to couple said second circuit node to said circuit ground.

15. A programmable logic array device as recited in claim 14 wherein said third and fourth switching elements are field effect transistors of opposite conductivity types.

16. A programmable logic array device as recited in claim 15 wherein said buffer means further includes a third inverter stage coupling said second circuit node to said inverter circuit output terminal.

17. A programmable logic array device as recited in claim 1 wherein said first row driver means includes a tri-state driver circuit comprising:

means forming a circuit input terminal for receiving said buffered signal, and a circuit output terminal;

a first field effect transistor means responsive to a buffered signal of a first signal state applied to said circuit input terminal and operative to couple said circuit output terminal to a source of potential of a first voltage, said first transistor means having its well region normally connected to said first source of potential;

a second field effect transistor means responsive to a buffered signal of a second signal state applied to said circuit input terminal and operative to couple said circuit output terminal to circuit ground;

gating means responsive to operating mode signals and operative to selectively disable said first and second transistor means; and

a switching device responsive to a first control signal and operative to couple said well region of said first transistor means to a second source of potential of a second voltage substantially greater in magnitude than said first voltage whereby said circuit output terminal may be driven by another signal source to a signal level greater than said first voltage.

18. A programmable logic array device as recited in claim 17 wherein said first transistor means is a P-channel device and said second transistor means is an N-channel device, and said gating means includes an inverter and a switching transistor responsive to a second control signal, said inverter being operative to invert said buffered signal and said switching transistor being operative to couple the inverted signal to the gate of said P-channel transistor, and a NOR gate responsive to a third control signal and said buffered signal and coupled between said circuit input terminal and the gate of said N-channel transistor.

19. A programmable logic array device as recited in claim 1 and further comprising:

means forming a second programmable AND array having a plurality of memory cells arranged in addressable rows and columns and which can be individually programmed to contain logic data;

second input circuit means for receiving a second input signal and for developing a second buffered signal corresponding thereto;

second row driver means responsive to said second buffered signal and operative to interrogate a first particular row of said second AND array memory cells and to cause said second AND array to output signals corresponding to the data contained therein;

second sensing means for sensing the signals output by said second AND array and for developing a corresponding second data signal which is the logical OR of the signals output by said second AND array;

second signal storage means for receiving and temporily storing said second data signal;

second output terminal means; and

second switching means responsive to a control signal and operative to couple either said second data signal or a data signal temporarily stored in said second signal storage means to said second output terminal means.

20. A programmable logic array device as recited in claim 19 and further comprising third row driver means responsive to a signal input thereto and operative to interrogate another particular row of said memory cells in said second AND array and to cause said second AND array to output other data signals corresponding to the data contained therein to said second sensing means for developing another data signal.

21. A programmable logic array device as recited in claim 20 wherein said first switching means is also operative to couple either the data signal output by said first sensing means or a data signal temporarily stored in said first signal storage means into said third row driver means.

22. A programmable logic array device as recited in claim 21 wherein said first switching means includes an output multiplexing device for connecting either the output of said first sensing means or a data signal temporarily stored in said first storage means to said first output terminal means.

23. A programmable logic array device as recited in claim 22 wherein said first switching means further includes a feedback multiplexing circuit operative to couple either the output of said first sensing means, a data signal temporarily stored in said first signal storage means, or data appearing at said first output terminal means to said third row driver means.

24. A programmable logic array device as recited in claim 23 wherein said memory cells are formed using EPROM technology.

25. A programmable logic array device as recited in claim 24 wherein said memory cells are formed using EEPROM technology.

26. A programmable logic array device as recited in claim 23 wherein said input circuit means includes a level shifting inverter circuit comprising:

means forming an input terminal for receiving a voltage signal having first and second states;

a level shifting inverter stage including,

a first switching element coupled between a voltage source and a first circuit node, said first switching element being responsive to said voltage signal and operative to switch between a conducting state when said voltage signal is in said first state and a non-conducting state when said voltage signal is in said second state,

a resistive impedance means coupling said first switching element to said voltage source,

a capacitive impedance means coupled between the junction of said resistive impedance means and said first switching element and circuit ground,

a second switching element coupled between said first circuit node and circuit ground, said second switching element being responsive to said voltage signal and operative to switch between a non-conducting state when said voltage signal is in said first state and a conducting state when said voltage signal is in said second state;

means forming an inverter circuit output terminal; and

buffer means coupling said first circuit node to said inverter circuit output terminal wherein said resistive impedance means assists in the switching of said first switching element from said conducting state to said non-conducting state, and wherein said capacitive impedance means serves to improve the switching speed of said first switching element as it switches from said non-conducting state to said conducting state.

27. A programmable logic array device as recited in claim 23 wherein said first row driver means includes a tri-state driver circuit comprising:

means forming a circuit input terminal for receiving said buffered signal, and a circuit output terminal;

a first field effect transistor means responsive to a buffered signal of a first signal state applied to said circuit input terminal and operative to couple said circuit output terminal to a source of potential of a first voltage, said first transistor means having its well region normally connected to said first source of potential;

a second field effect transistor means responsive to a buffered signal of a second signal state applied to said circuit input terminal and operative to couple said circuit output terminal to circuit ground;

gating means responsive to operating mode signals and operative to selectively disable said first and second transistor means; and

a switching device responsive to a first control signal and operative to couple said well region of said first transistor means to a second source of potential of a second voltage substantially greater in magnitude than said first voltage whereby said circuit output terminal may be driven by another signal source to a signal level greater than said first voltage.