Automatic train control apparatus

• US 4,618,930 A
• Filed: 10/16/1984
• Issued: 10/21/1986
• Est. Priority Date: 10/03/1980
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Toyota, Eiichi, Ueno, Masahiro, Tashiro, Korefumi
• Primary Examiner(s): Chin, Gary
• Application Number:
  US06/661,388
• Time in Patent Office: 735 Days
• Field of Search: 364/424, 364/426, 246/182 R, 246/182 A, 246/182 B, 246/122 C, 246/187 R, 371/37
• US Class Current: 701/20
• CPC Class Codes: B61L 15/0062 On-board target speed calculation or supervision
• CPC Class Codes: Y02T 10/72 Electric energy management in electromobility

Abstract

In an ATC apparatus, an ROM stores a plurality of parameters used for identification of an ATC signal. These parameters are sequentially read out from the ROM and applied to a ring-arithmetic type frequency pattern generating circuit to be converted into a plurality of pulse trains having respective reference frequencies. These pulse trains are then sequentially applied to a ring-arithmetic type frequency comparison circuit and are compared with the frequency-modulated ATC signal in a time division mode so as to identify the speed limit indicated by the ATC signal. The frequency pattern generating circuit generates also a pulse train corresponding to the speed limit. The frequency comparison circuit executes also comparison between the frequency of the pulse train indicative of the speed limit and that of a pulse train indicative of the detected train speed, and an ATC brake instruction signal is generated when the result of comparison proves that the detected train speed exceeds the speed limit. The frequency pattern generating circuit and the frequency comparison circuit are included in a single LSI.

Claims

1. An automatic train control apparatus responsive to a frequency-modulated ATC signal, which is transmitted from a transmitter disposed along the train track and indicates one of a plurality of selected speed limits, for limiting the speed of the train as indicated by a speed signal received from a speed detector to a speed not higher than the speed limit indicated by the ATC signal, comprising:

memory means including a read-only memory for storing digital codes corresponding to respective ones of said plurality of selected speed limits; and

a large-scale integrated circuit connected to said read-only memory, and including;

(a) signal input means for receiving an ATC signal from said transmitter and said speed signal having a frequency corresponding to the train speed from said speed detector,

(b) speed limit detecting means connected to said signal input means and said read-only memory for identifying the speed limit indicated by said received ATC signal and for reading out of said read-only memory a digital code corresponding to said identified speed limit,

(c) speed correlation means for comparing the speed limit indicated by the received ATC signal with the actual train speed indicated by said received speed signal, including first signal mode matching means connected to said signal input means and said speed limit detecting means for converting the mode of said speed signal or the mode of said digital code read out of said read-only memory to produce a speed signal and a speed limit signal whose signals modes correspond to each other, and comparison means connected to said signal mode matching means for producing an output when said speed signal exceeds said speed limit signal, and

(d) output means for delivering a false instruction signal in response to the output of said comparison means so as to prevent the train from exceeding the speed indicated by said ATC signal.

2. An automatic train control apparatus according to claim 1, wherein said read-only memory stores, for each of said selected speed limits, a first digital code representing a parameter for identifying the speed limit and a second digital code representing a parameter of the speed limit, and wherein said speed limit detecting means includes means for identifying the speed limit indicated by the receviced ATC signal on the basis of the first digital codes stored in said read-only memory.

3. An automatic train control apparatus according to claim 2, wherein said memory means includes means for successively reading-out said first digital codes and wherein said identifying means includes second signal mode matching means connected to said signal input means and said read-only memory for converting the mode of said ATC signal or the mode of said first digital codes to produce a first output signal and a sequence of second output signals all having the same signal mode and correspond to said ATC signal and said first digital codes, respectively, correlating means for correlating said first output signal with said sequence of second output signals, and output means connected to said correlating means for identifying the first digital code which corresponds to said ATC signal and for generating an address signal for reading out of said read-only memory the second digital code correspond to the same speed limit as the first digital code identified by said correlating means.

4. An automatic train control apparatus according to claim 3, wherein said comparison means in said speed correlation means and said correlating means in said identifying means are provided by means including a single comparison circuit for executing the functions of the comparison means and the correlating means in a time division mode.

5. An automatic train control apparatus according to claim 1, wherein said first signal mode matching means includes means for converting said digital code read out of said read-only memory to a frequency signal, and said comparison means includes means for comparing the frequency of said speed signal to the frequency of said frequency signal from said converting means.

6. An automatic train control apparatus according to claim 1, wherein said first signal mode matching means includes means for converting said speed signal from said signal input means to a digital code, and said comparison means includes means for comparing the digital code from said converting means with the digital code read out of said read-only memory means.

7. An automatic train control apparatus according to claim 3, wherein said second signal mode matching means includes means for converting said second digital codes read out of said read-only memory to frequency signals corresponding to the frequencies of said ATC signals for different ones of said plurality of selected speed limits, and said correlating means includes means for effecting a successive comparison between said ATC signal received by said signal input means and the frequency signals produced by said converting means.

8. An automatic train control apparatus according to claim 3, wherein said read-only memory also stores an error check code which is read out with said digital codes, and said large-scale integrated circuit further includes error detecting means for detecting an error in the first and second digital codes read out of said read-only memory on the basis of said error check code.

9. An automatic train control apparatus according to claim 8, wherein said error check code includes a CRC code added to said digital codes, and said error detecting means includes a CRC error check circuit.

10. An automatic train control apparatus for receiving a frequency-modulated ATC signal transmitted from a transmitter disposed along the track, for comparing the speed limit indicated by the received ATC signal with the actual train speed detected by a speed detector and for delivering a brake instruction signal when the detected speed exceeds the speed limit so as to run the train at a speed not higher than the speed limit, said automatic train control apparatus comprising means for generating a plurality of reference signals used for identifying the speed limit indicated by said ATC signal, first comparing means for comparing said ATC signal sequentially with said plural reference signals and for producing an output signal identifying the reference signal which corresponds to said ATC signal, means for generating one of a plurality of speed limit signals corresponding to the speed limit indicated by said ATC signal in response to the output signal appearing from said first comparing means, second comparing means for comparing a train speed-indicative signal from said speed detector with said speed limit signal, said reference signals generating means and said speed limit signal generating means including means for storing parameters corresponding to a plurality of predetermined reference signals which are compared with said ATC signal to identify the speed limit included in said ATC signal and speed limit signal, and means for reading out said parameters while effecting a matching between the signal mode of the read-out parameters and that of said ATC signal and said train speed-indicative signal, and output means for delivering a brake instruction signal in accordance with the result of said comparison by said second comparing means, so as to prevent the train from exceeding the speed indicated by said ATC signal.

11. An automatic train control apparatus as claimed in claim 10, wherein said first and second comparing means are provided by single comparing means which executes the functions of said first and second comparing means in a time division mode.

12. An automatic train control apparatus as claimed in claim 10, wherein said plural reference signals, said speed limit signals and said train speed-indicative signal are frequency signals, and said first and second comparing means comprise frequency comparing means.

13. An automatic train control apparatus as claimed in claim 10, wherein said reference signal generating means and said speed limit signal generating means are provided by single signal generating means which executes the functions of said reference signal generating means and said speed limit signal generating means in a time division mode.

14. An automatic train control apparatus responsive to a frequency-modulated ATC signal, which is transmitted from a transmitter disposed along the train track and indicates one of a plurality of selected speed limits, for limiting the speed of the train as indicated by a speed signal received from a speed detector to a speed not higher than the speed limit indicated by the ATC signal, comprising:

memory means including a read-only memory for storing digital codes corresponding to respective ones of said plurality of selected speed limits; and

a large-scale integrated circuit connected to said read-only memory, and including;

(a) signal input means for receiving an ATC signal from said transmitter and said speed signal having a frequency corresponding to the train speed from said speed detector,

(b) means for identifying the speed limit included in the ATC signal, connected to said read-only memory for storing a first parameter which is a comparison reference value for identifying the speed limit, said speed limit identifying means comprising first signal mode converting means for converting said first parameter into a signal mode comparable to the ATC signal, second signal mode converting means for converting the ATC signal into a signal mode comparable to said first parameter, and a comparison circuit for comparing the converted first parameter with the ATC signal;

(c) speed correlation means for determining whether or not a train speed exceeds the identified speed limit, connected with said read-only memory for storing a second parameter which is a reference value for the speed limit comparison corresponding to the identified speed limit, said speed correlation means comprising third signal mode converting means for converting said second parameter into a signal mode comparable to a speed signal from speed detector, fourth signal mode converting means for converting said speed signal into a signal mode comparable to said second parameter, and a comparison circuit for comparing said converted second parameter with said speed signal to produce an output signal,

(d) output means for delivering a false instruction signal in response to said output signal of said comparison circuit so as to prevent the train from exceeding the speed indicated by said ATC signal.