Dual port access circuit with automatic asynchronous contention resolving capability
First Claim
1. A circuit for producing a pair of contention resolved output signals from first and second conflicting access request signals comprising:
- (a) first and second cross-coupled, triple input main combinational logic elements each having an input terminal that is separately connected for receiving the first and second request signals, respectively;
(b) first and second bistable logic elements each respectively connected for delivering to another separate input terminal of the first and second main logic elements, respectively, first and second priority status signals representative of the instantaneous priority of access status of the access request signals.
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Abstract
Two microprocessors, which may be operating asynchronously, share a random access memory (RAM) array; that is, at any one moment of time, either microprocessor can seek access to the RAM but only one of them can actually gain access at a time. Priority of access to the RAM is controlled by a dual port contention-resolving access circuit which enables such access alternately to the two microprocessors when both are seeking (overlapping) access, subject to the stipulation when neither microprocessor is accessing the RAM that the very next access will be allocated by the circuit on a first-come first-served basis, and will be allocated to a preselected one of the microprocessors if both microprocessors will commence to seek access precisely at the same time.
45 Citations
32 Claims
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1. A circuit for producing a pair of contention resolved output signals from first and second conflicting access request signals comprising:
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(a) first and second cross-coupled, triple input main combinational logic elements each having an input terminal that is separately connected for receiving the first and second request signals, respectively; (b) first and second bistable logic elements each respectively connected for delivering to another separate input terminal of the first and second main logic elements, respectively, first and second priority status signals representative of the instantaneous priority of access status of the access request signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A circuit, (e.g., 30) comprising:
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(a) first and second cross-coupled main combinational logic elements (e.g., G1 and G2) each having an output terminal separately connected, respectively, to a different one of first and second nodes (e.g., N1 and N2); and (b) third and fourth cross-coupled auxiliary combinational logic elements (e.g., G3 and G4) each having an output terminal separately connected, respectively, to a different one of the first and second nodes (e.g., N1 and N2), the output driving strengths of the third and fourth logic elements (e.g., G3 and G4) being significantly weaker, respectively, than those of the first and second logic elements (e.g., G1 and G2), an input terminal of both the first and of the third logic elements (e.g., G1 and G3) connected for receiving a first priority status signal (e.g., Q1), and an input terminal of both the second and fourth logic elements (e.g., G2 and G4) connected for receiving a second priority status signal (e.g., Q2). - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A contention resolving circuit (e.g., 30) comprising:
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(a) first and second cross-coupled main combinational logic elements (e.g., G1 and G2) each having an output terminal separately connected, respectively, to a different one of first and second nodes (e.g., N1 and N2); (b) third and fourth cross-coupled auxiliary combinational logic elements (e.g., G3 and G4) each having an output terminal separately connected, respectively, to a different one of the first and second nodes (e.g., N1 and N2), the output driving strengths of the third and fourth logic elements (e.g., G3 and G4) being significantly weaker, respectively, than those of the first and second logic elements (e.g., G1 and G2); and (c) first and second bistable logic elements (e.g., FF1, FF2) each respectively connected for delivering to a separate input terminal (e.g., A2, B2) of the first and second main logic elements (e.g., G1, G2), respectively, first and second priority status signals (Q1, Q2) representative of the instantaneous priority of access status of the access request signals (e.g., CS1=0, CS2=0). - View Dependent Claims (25, 26)
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27. A dual port access enabling circuit comprising:
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(a) first and second cross-coupled combinational logic elements (e.g., G1 and G2); (b) third and fourth cross-coupled combinational logic elements (e.g., G3 and G4) of weaker driving strengths than those of the first and second logic elements, an output terminal of each of the third logic elements (e.g., G1 and G3) being connected to a first output node (e.g., N1), an output terminal of each of the second and fourth logic elements (e.g., G2 and G4) being connected to a second output node (e.g., N2), an input terminal of each of the first and second elements (e.g., G1 and G2) being connected for receiving, respectively, first and second access request signals, an input terminal of each of the third and fourth elements (e.g., G3 and G4) being connected for receiving, respectively, the first and second access request signals delayed by differing first and second amounts of time (e.g., Δ
1 and Δ
2), respectively; and(c) first and second bistable logic elements (e.g., FF1 and FF2) connected for sending to the first and second combinational logic elements (e.g., G1 and G2), respectively, first and second priority status signals (e.g., Q1 and Q2).
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28. A contention resolving access circuit comprising:
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(a) first and second main gates (e.g., G1, G2) to be supplied respectively with first and second input signals (e.g., CS1, CS2) contending for access, designed so that the one main gate (say G1) which happens to be supplied first in time with an input signal (say CS1=1) is selectively enabled; and (b) bistable means (e.g., G5 , FF1) supplied with a signal (e.g., CE1PD) derived from an output signal (e.g., CE1P) of the selectively enabled gate (say G1) for disabling the one gate (say G1) immediately after lapse of a prescribed interval of time after it has been enabled and for immediately subsequently maintaining it disabled until the input signal (say CS1) to that gate (say G1) terminates. - View Dependent Claims (29, 30)
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31. A circuit for producing a pair of contention resolved output signals from first and second conflicting access requests signals, the circuit being connected for delivering the contention resolved output signals to target circuitry, comprising:
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(a) first and second cross-coupled, triple input main combinational logic elements each having an input terminal that is separately connected for receiving the first and second request signals, respectively; (b) first and second bistable logic elements each respectively connected for delivering to another separate input terminal of the first and second main logic elements, respectively, first and second priority status signals representative of the instantaneous priority of access status of the access request signals. - View Dependent Claims (32)
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Specification