Demodulator for multiphase PSK or multilevel QAM signals
First Claim
1. A demodulation device comprising:
- phase detector means for demodulating a multiphase PSK carrier wave or a multilevel QAM wave into a baseband signal;
A/D converter means for sampling the output signal of said phase detector means in response to a timing signal and converting it to digital signals;
means responsive to said digital signals from said A/D converter means for supplying a carrier wave to said phase detector means;
timing synchronizing means for generating a timing signal representing a timing of sampling of said A/D converter means, and timing synchronizing means having a timing signal generator, a phase of which is controlled by a predetermined phase control signal, which generates the timing signal, and which includes a low-pass filter and a voltage controlled oscillator adapted to receive the output from said filter and to provide an output in at least a loop with a loop parameter, a polarity identification circuit for receiving a first predetermined signal among said digital signals from said A/D converter means, identifying a polarity of a differential coefficient of the baseband signal at a sampling point of said A/D converter means and generating a polarity identification signal, and logic circuit means for receiving and processing according to a predetermined logic the polarity identification signal from said polarity identification circuit and a second predetermined signal among said digital signals from said A/D converter means and generating and supplying to said timing signal generator a phase control signal representing a deviation of an actual sampling point of the baseband signal from an optimal sampling point; and
carrier asynchronism detecting means for detecting an asynchronism state of said carrier wave supplying means and supplying to said timing synchronizing means a signal which controls said loop parameter of said timing synchronizing means.
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Accused Products
Abstract
In a demodulation circuit, a timing synchronizing circuit generates a timing signal representing a sampling timing of an A/D converter and has a timing signal generator, a polarity identification circuit and a logic circuit. The timing signal generator is phase-controlled by a phase control signal and generates a timing signal. The polarity identification circuit identifies a polarity of a differential coefficient of the baseband signal at a sampling point of the A/D converter and generates a polarity identification signal. Upon logic processing, the logic circuit supplies to the timing signal generator the phase control signal representing a deviation of an actual sampling point of the baseband signal from an optimal sampling point. A carrier asynchronism detection circuit detects an asynchronism state of a carrier regenerating circuit and supplies to the timing synchronizing circuit a signal which changes its loop parameter.
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Citations
3 Claims
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1. A demodulation device comprising:
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phase detector means for demodulating a multiphase PSK carrier wave or a multilevel QAM wave into a baseband signal; A/D converter means for sampling the output signal of said phase detector means in response to a timing signal and converting it to digital signals; means responsive to said digital signals from said A/D converter means for supplying a carrier wave to said phase detector means; timing synchronizing means for generating a timing signal representing a timing of sampling of said A/D converter means, and timing synchronizing means having a timing signal generator, a phase of which is controlled by a predetermined phase control signal, which generates the timing signal, and which includes a low-pass filter and a voltage controlled oscillator adapted to receive the output from said filter and to provide an output in at least a loop with a loop parameter, a polarity identification circuit for receiving a first predetermined signal among said digital signals from said A/D converter means, identifying a polarity of a differential coefficient of the baseband signal at a sampling point of said A/D converter means and generating a polarity identification signal, and logic circuit means for receiving and processing according to a predetermined logic the polarity identification signal from said polarity identification circuit and a second predetermined signal among said digital signals from said A/D converter means and generating and supplying to said timing signal generator a phase control signal representing a deviation of an actual sampling point of the baseband signal from an optimal sampling point; and carrier asynchronism detecting means for detecting an asynchronism state of said carrier wave supplying means and supplying to said timing synchronizing means a signal which controls said loop parameter of said timing synchronizing means. - View Dependent Claims (2, 3)
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Specification