Demodulator for multiphase PSK or multilevel QAM signals

• US 4,620,159 A
• Filed: 08/27/1985
• Issued: 10/28/1986
• Est. Priority Date: 08/27/1984
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yagi, Manabu, Yoshida, Yasuharu
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Mis, D. C.
• Application Number:
  US06/769,922
• Time in Patent Office: 427 Days
• Field of Search: 329/50, 329/122, 329/124, 329/126, 329/135, 375/39, 375/81, 375/82, 375/83, 375/120, 455/214, 455/337
• US Class Current: 329/309
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions

Abstract

In a demodulation circuit, a timing synchronizing circuit generates a timing signal representing a sampling timing of an A/D converter and has a timing signal generator, a polarity identification circuit and a logic circuit. The timing signal generator is phase-controlled by a phase control signal and generates a timing signal. The polarity identification circuit identifies a polarity of a differential coefficient of the baseband signal at a sampling point of the A/D converter and generates a polarity identification signal. Upon logic processing, the logic circuit supplies to the timing signal generator the phase control signal representing a deviation of an actual sampling point of the baseband signal from an optimal sampling point. A carrier asynchronism detection circuit detects an asynchronism state of a carrier regenerating circuit and supplies to the timing synchronizing circuit a signal which changes its loop parameter.

Claims

1. A demodulation device comprising:

phase detector means for demodulating a multiphase PSK carrier wave or a multilevel QAM wave into a baseband signal;

A/D converter means for sampling the output signal of said phase detector means in response to a timing signal and converting it to digital signals;

means responsive to said digital signals from said A/D converter means for supplying a carrier wave to said phase detector means;

timing synchronizing means for generating a timing signal representing a timing of sampling of said A/D converter means, and timing synchronizing means having a timing signal generator, a phase of which is controlled by a predetermined phase control signal, which generates the timing signal, and which includes a low-pass filter and a voltage controlled oscillator adapted to receive the output from said filter and to provide an output in at least a loop with a loop parameter, a polarity identification circuit for receiving a first predetermined signal among said digital signals from said A/D converter means, identifying a polarity of a differential coefficient of the baseband signal at a sampling point of said A/D converter means and generating a polarity identification signal, and logic circuit means for receiving and processing according to a predetermined logic the polarity identification signal from said polarity identification circuit and a second predetermined signal among said digital signals from said A/D converter means and generating and supplying to said timing signal generator a phase control signal representing a deviation of an actual sampling point of the baseband signal from an optimal sampling point; and

carrier asynchronism detecting means for detecting an asynchronism state of said carrier wave supplying means and supplying to said timing synchronizing means a signal which controls said loop parameter of said timing synchronizing means.

2. A device according to claim 1, wherein the output signal from said carrier asynchronism detection means is supplied to said low-pass filter in said timing signal generator to switch bandwidth parameters of said low-pass filter between carrier asynchronising and synchronizing modes.

3. A device according to claim 1, wherein said low-pass filter comprises a secondary delay/lead filter consisting of a series circuit of first and second resistors and a capacitor and a parallel circuit of a diode and a third resistor which is connected between one end of said capacitor and a reference potential terminal, one end of said first resistor being connected to an output terminal of said logic circuit means, a joint between said first and second resistors being connected to an input terminal of said voltage-controlled oscillator in said timing signal generator, a joint between said capacitor and one end of said parallel circuit being connected to an output terminal of said carrier asynchronism detection means, and the other end of said parallel circuit being connected to said reference potential terminal.