Method for successive approximation A/D conversion

• US 4,620,179 A
• Filed: 08/30/1985
• Issued: 10/28/1986
• Est. Priority Date: 08/29/1983
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Bacrania, Kanti, Cooper, Frank R.
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US06/771,160
• Time in Patent Office: 424 Days
• Field of Search: 340/347 AD
• US Class Current: 341/156
• CPC Class Codes: H03M 1/0697 in time, e.g. using additional comparison cycles
• CPC Class Codes: H03M 1/462 Details of the control circuitry, e.g. of the successive approximation register

Abstract

A method of successive approximation A/D conversion employing an N bit internal D/A converter and an N bit SAR is provided wherein the first X bits are approximated to within less than the desired accuracy for N bit successive approximation while the last Y bits are approximated to within at least the desired accuracy for N bit successive approximation. After the Xth bit approximation, the A/D converter may be allowed sufficient time to settle to within the desired accuracy for N bit approximation during an error correction stage which increments or decrements the digital signal for the first X bits.

Claims

1. A method of high speed digitizing of analog input signals to N bit digital numbers in a successive approximation analog to digital converter means having an internal digital to analog converter means and successive approximation register means both scaled for N bits comprising:

a. supplying input signals to be digitized;

b. successively approximating the states of the first X bits, where X is less than N and greater than one, at a rate which provides less than the desired accuracy of conversion for the first X bits of N bits of successive approximation conversion, but which provides at least the desired accuracy of conversion for the last Y bits, where Y plus X equals N;

c. allowing the input signal to settle to at least the desired accuracy for N bits of successive approximation after successively approximating the Xth bit;

d. comparing the input signal to a signal which is representative of said first X bits and digitally incrementing or decrementing at least one of said X bits in response to said comparison to correct for conversion inaccuracies; and

e. successively approximating the states of the last Y bits, at said rate which provides at least the desired accuracy of conversion for said last Y bits, to complete the digitizing process.

2. The method of high speed digitizing according to claim 1, wherein said comparison is of the currents of said respective signals.

3. The method of high speed digitizing according to claim 1, wherein the states of said first X bits are successively approximated to within the desired accuracy of X bits of successive approximation conversion as if said internal digital to analog converter means and successive approximation register means were both scaled for X bits only.

4. The method of high speed digitizing according to claim 1, wherein N is twelve, X is eight, and Y is four.

5. A successive approximation analog to digital converter means for high speed digitizing of analog input signals to N bit digital numbers comprising:

input means for receiving analog input signals to be digitized;

comparator means connected to said input means for receiving analog input signals and for providing output signals as a function of the difference between first and second signals applied thereto;

N bits successive approximation register means connected to said comparator means for producing digital output signals successively approximating the states of N bits of said digital numbers as a function of said output signals from said comparator means;

N bit digital to analog converter means, connected to said N bit successive approximation register means and said comparator means, for producing analog signals as a function of the states of said N bits; and

X bit counter means connected between the first X bits of the N bit successive approximation register means and the first X bits of the N bit digital to analog converter means, where X is less than N and greater than one;

wherein said N bit successive approximation register means includes means for successively approximating the states of the first X bits at a rate which provides less than the desired accuracy of conversion for the first X bits of N bits of successive approximation conversion, but which provides at least the desired accuracy of conversion for the last Y bits, where Y plus X equals N;

means for allowing the input signal to settle to at least the desired accuracy for N bits of successive approximation after successively approximating the Xth bit;

means for comparing the input signal to a signal which is representative of said first X bits and means for digitally incrementing or decrementing said X bit counter in response to said comparison to correct for conversion inaccuracies; and

means for successively approximating the states of the last Y bits, at said rate which provides at least the desired accuracy of conversion for said last Y bits, to complete the digitizing process.

6. The analog to digital converter means according to claim 5, wherein said correction means includes said comparator means and permits said comparator means to settle to at least the desired accuracy for N bit successive approximation conversion when correcting for conversion inaccuracies resulting up to said Xth bit of successive approximation.

7. The analog to digital converter means according to claim 6, wherein said correction means alters said digital signal produced in response to successive approximation to the Xth bit by increasing or decreasing the least significant bit of that digital signal prior to continuing successive approximation through the remaining N-X bits.

8. The analog to digital converter means according to claim 5, wherein the digital states of said X bits are successively approximated to within the desired accuracy of X bits of successive approximation conversion as if said successive approximation register means and said digital to analog converter means were scaled to X bits rather than N bits.

9. The analog to digital converter means according to claim 5, wherein N is twelve and X is eight.

10. The analog to digital converter means according to claim 5, wherein the settling time for successive approximation conversion at each of the N bit levels is substantially uniform.