Video display system

• US 4,620,289 A
• Filed: 02/23/1984
• Issued: 10/28/1986
• Est. Priority Date: 04/25/1983
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard
• Primary Examiner(s): Gruber, Felix D.
• Assistant Examiner(s): Herndon, H. R.
• Application Number:
  US06/583,074
• Time in Patent Office: 978 Days
• Field of Search: 364/514, 364/521, 364/518, 358/11, 358/18, 340/720, 340/723, 340/750, 340/793
• US Class Current: 345/559
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/42 characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen

Abstract

In this apparatus, a composite memory 5 includes a managing memory (5g) containing for each line of the frame to be displayed, a word made up of information relating to the composition of the line in question. This information can define a base color, the number of memory planes, and, if appropriate, a base address of a zone of a zone memory (5z) which contains the data relating to the parts of the image which contain only typographic or graphic information. If the number of planes is equal to zero, said base color becomes a constant background color in the totality of the line to be displayed. The contents of the control memory are read out, word by word, from the control memory at the frequency of the line synchronization signal for the screen.

Application to teletext systems.

Claims

1. A control apparatus for a raster scan video display having a plurality of video display lines comprising:

a composite memory for storing data indicative of a video display including

a managing memory having a plurality of line composition data words, one line composition data word for each video display line, each line composition data word indicating the composition of the data for the corresponding video display line, and

a zone memory having a plurality of memory zones, one memory zone corresponding to each video display line, each memory zone including image data indicative of the image data having the corresponding video display line, said image data having the composition indicated by the corresponding line composition data word;

a central processing unit connected to said composite memory for controlling the composition of the video display by controlling the data stored in said managing memory and said zone memory;

a time base unit for generating time base signals in synchronization with the raster scan of the video display; and

a video display processor connected to said composite memory and said time base unit for generating at least one video display control signal for formation of the video display by recall of said line composition data word from said managing memory corresponding to the current video display line, recalling said image data from said zone memory corresponding to successive pixels of the current video display line and forming said at least one video control signal in accordance with said recalled image data for each pixel of the current video display line by interpreting said image data in accordance with said composition indicated by said recalled line composition data word.

2. A control apparatus for a raster scan video display as claimed in claim 1, wherein:

each line composition data word of said managing memory includes data indicative of a background color, and data indicative of the number of memory planes of the image data corresponding to the video display line; and

each memory zone of said zone memory includes image data having the number of memory planes indicated by said corresponding line composition data word.

3. A control apparatus for a raster scan video display as claimed in claim 1, wherein:

each line composition data word of said managing memory includes data indicative of a background color, data indicative of the number of memory planes of the image data corresponding to the video display line, and data indicative of the base address of the memory zone within said zone memory corresponding to said line composition data word; and

each memory zone of said zone memory starts at an address corresponding to said base address indicated by said corresponding line composition data word, and includes image data having the number of memory planes indicated by said corresponding line composition data word.

4. A control apparatus for a raster scan video display as claimed in claim 3, wherein:

said video display processor includes

a base color register loaded at the start of each video display line with the base color indicated by the corresponding line composition data word, and

a plane number register loaded at the start of each video display line with the number of memory planes indicated by said corresponding line composition data word.

5. A control apparatus for a raster scan video display as claimed in claim 4, wherein:

said video display processor further includes

a plurality of shift registers equal to the maximum number of memory planes of any zone memory having a predetermined number of stages connected to said time base unit for shifting data at a rate corresponding to the pixel rate of said video display, each of said shift registers having a serial input connected to a corresponding bit of said base color register, a parallel input for receiving image data from said corresponding memory zone of a single color plane of said predetermined number of adjacent pixels, a parallel load control input and a serial output,

a memory plane control circuit connected to said time base unit, said plane number register and said parallel load control input of each of said shift registers for enabling the parallel loading of a predetermined set of said shift registers equal in number to said number of memory planes stored in said plane number register at a rate equal to said pixel rate divided by said predetermined number of stages of said shift registers,

a color palette connected to said serial outputs of said shift registers having color data words stored at a plurality of address locations therein for forming said at least one video control signal by recall of color data words from addresses corresponding to said outputs of said shift registers, whereby said address corresponds to said image data parallel loaded into each of said selected set of shift registers and said base color serial loaded into the other shift registers.

6. A control apparatus for a raster scan video display as claimed in claim 5, wherein:

said video display processor further includes

a plurality of waiting registers equal in number to the number of said shift registers, each connected to said zone memory and to a corresponding shift register, for temporarily storing said image data from said corresponding memory zone of a single color plane of said predeterminednumber of adjacent pixels in advance of parallel loading of said image data into said corresponding shift register.

7. A control apparatus for a raster scan video display comprising:

a composite memory for storing data indicative of a video display including

a managing memory having a plurality of line composition data words, one line composition data word for each video display line, each line composition data word indicating the composition of the data for the corresponding video display line, and

a zone memory having a plurality of memory zones, one memory zone corresponding to each video display line, each memory zone including image data indicative of the image of the corresponding video display line, said image data having the composition indicated by the corresponding line composition data word;

a time base unit for generating time base signal in synchronization with the raster scan of the video display; and

a video display processor connected to said composite memory and said time base unit for generating at least one video display control signal for formation of the video display by recall of said line composition data word from said managing memory corresponding to the current video display line, recalling said image data from said zone memory corresponding to successive pixels of the current video display line and forming said at least one video control signal in accordance with said recalled image data for each pixel of the current video display line by interpreting said image data in accordance with said composition indicated by said recalled line composition data word.

8. A control apparatus for a raster scan video display as claimed in claim 7, wherein:

each line composition data word of said managing memory includes data indicative of a background color, data indicative of the number of memory planes of the image data corresponding to the video display line, and data indicative of the base address of the memory zone within said zone memory corresponding to said line composition data word; and

each memory zone of said zone memory starts at an address corresponding to said base address indicated by said corresponding line composition data word, and includes image data having the number of memory planes indicated by said corresponding line composition data word.

9. A control apparatus for a raster scan video display as claimed in claim 8, wherein:

said video display processor includes

a base color register loaded at the start of each video display line with the base color indicated by the corresponding line composition data word,

a plane number register loaded at the start of each video display line with the number of memory planes indicated by said corresponding line composition data word,

a plurality of shift registers equal to the maximum number of memory planes of any zone memory having a predetermined number of stages connected to said time base unit for shifting data at a rate corresponding to the pixel rate of said video display, each of said shift registers having a serial input connected to a corresponding bit of said base color register, a parallel input for receiving image data from said corresponding memory zone of a single color plane of said predetermined number of adjacent pixels, a parallel load control input and a serial output,

a memory plane control circuit connected to said time base unit, said plane number register and said parallel load control input of each of said shift registers for enabling the parallel loading of a predetermined set of said shift registers equal in number of said number of memory planes stored in said plane number register at a rate equal to said pixel rate divided by said predetermined number of stages of said shift registers,

a color palette connected to said serial outputs of said shift registers having color data words stored at a plurality of address locations therein for forming said at least one video control signal by recall of color data words from addresses corresponding to said outputs of said shift registers, whereby said address corresponds to said image data parallel loaded into each of said selected set of shift registers and said base color serial loaded into the other shift registers.