SIMD machine using cube connected cycles network architecture for vector processing
First Claim
1. A single instruction multiple data processor comprising:
- a plurality of processing elements, interconnected in a Cube Connected Cycle Network design and using interprocessor communication links which carry one bit at a time in both directions simultaneously;
controller means for controlling each of said plurality of processor elements which feeds each of said processor elements identical local memory addresses, identical switching control bits, identical Boolean function selection codes, and distinct activation control bits, depending on each of said processor'"'"'s position in said Cube Connected Cycles Network in a prescribed fashion; and
a plurality of input/output devices connected to said network by a plurality of switching devices wherein,each of said plurality of processing elements comprises;
two single-bit accumulator registors (A, B);
two Boolean function generator units, each of which computes any one of 28 possible Boolean functions of three Boolean variables as specified by Boolean function codes sent 2 at a time by said controller to each of said processing elements;
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Abstract
A single instruction, multiple data stream parallel computer using bit-serial arithmetic whereby the machine'"'"'s basic operation is performing Boolean operations on huge vectors of 0'"'"'s and 1'"'"'s. The machine utilizes an architectural approach whereby the memory of a conventional machine having 2k words each t bits long, is reorganized into p registers each 2k bits in length and adding processor logic to each bit position of the registers and a communication network being added which allows for the 2k pieces of processing logic to interact. This machine is capable of executing a wide variety of algorithms at a speed of 2k /p to 2k /p2 faster than conventional machines. The machine provides for an ability to handle a variety of algorithms by interconnecting the individual processor elements in a general interconnection network capable of performing a permutation of n bits held one in every processor element in a time of (O(log(n)).
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Citations
8 Claims
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1. A single instruction multiple data processor comprising:
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a plurality of processing elements, interconnected in a Cube Connected Cycle Network design and using interprocessor communication links which carry one bit at a time in both directions simultaneously; controller means for controlling each of said plurality of processor elements which feeds each of said processor elements identical local memory addresses, identical switching control bits, identical Boolean function selection codes, and distinct activation control bits, depending on each of said processor'"'"'s position in said Cube Connected Cycles Network in a prescribed fashion; and a plurality of input/output devices connected to said network by a plurality of switching devices wherein, each of said plurality of processing elements comprises; two single-bit accumulator registors (A, B); two Boolean function generator units, each of which computes any one of 28 possible Boolean functions of three Boolean variables as specified by Boolean function codes sent 2 at a time by said controller to each of said processing elements; - View Dependent Claims (3, 4, 5, 6, 8)
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2. switching circuit means controlled by said controller which select the three inputs to the logic function generators and to which switching circuitry provides that the output of one of said generators is fed to a first one of said registers (B) and the output of the other generator is fed to a second one of said registers (A) and an addressed memory cell of a local memory wherein said local memory consists of at least k bits and at most p bits where p is chosen to be appropriate to VLSI technology so that the space on a VLSI chip required by an entire processing element is at least one-half devoted to the processing elements'"'"'s memory.
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7. A single instruction multiple data processor comprising:
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a plurality of processing elements, interconnected in a Cube Connected Cycle Network design and using interprocessor communication links which carry one bit at a time in both directions simultaneously; controller means for controlling each of said plurality of processor elements which feeds each of said processor elements identical local memory addresses, identical switching control bits, identical Boolean function selection codes, and distinct activation control bits, depending on each of said processor'"'"'s position in said Cube Connected Cycles Network in a prescribed fashion; and a plurality of input/output devices connected to said network by a plurality of switching devices wherein, said cube connected cycles consist of Q * 2Q processing elements arranged in 2Q cycles of Q processing elements each, wherein each processing element X is numbered by a pair of Xc, Xp where Xc is the cycle number to which processing element X belongs and Xp is processing elements X'"'"'s position number within its cycle and wherein connections are provided between each processing element and its successor, predecessor and lateral neighbors defined between processing element (c, p) and the processing elements numbered (C, (p+1) mod Q), (C,(p-1) mod Q), and (D, p) such that the absolute value of C-D=2P.
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Specification