Method and apparatus for controlling a motor

• US 4,622,499 A
• Filed: 02/27/1985
• Issued: 11/11/1986
• Est. Priority Date: 02/27/1985
• Status: Expired due to Term

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Miniscribe Corporation
• Inventors: Freeman, John J., Squires, John P., Touchton, James J., Kronisch, Alan D.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Ro, Bentsu
• Application Number:
  US06/706,147
• Time in Patent Office: 622 Days
• Field of Search: 318/138, 318/254 A, 318/254, 318/313, 318/314, 318/439, 318/269, 318/696
• US Class Current: 318/400.04
• CPC Class Codes: H02P 6/06 Arrangements for speed regulation of a single motor wherein the motor speed is measured and compared with a given physical value so as to adjust the motor speed
• CPC Class Codes: H02P 6/17 and for generating speed information

Abstract

An n-phase DC motor is controlled by converting a motor speed command signal generated from a programmed CPU to a motor drive signal and using this motor drive signal to apply DC power to a selected phase of the motor, the amount of applied DC power being a function of the value of the motor speed command signal. Signals representing the position and/or speed of the motor are supplied to the CPU from which the CPU detects speed errors. The speed command signal then is modified to speed up or slow down the motor so as to reduce the detected errors.

Claims

1. A method of driving an n-phase DC motor, where n>

1, comprising the steps of operating a central processing unit (CPU) to generate a motor speed command signal in accordance with a predetermined programmed set of instructions;

converting said motor speed command signal to a motor drive signal;

selecting a respective phase of said DC motor to be energized;

applying DC power to the selected phase as a function of said motor drive signal;

supplying to said CPU signals representing the position or speed of said DC motor;

operating said CPU to detect both rapidly changing and slowly changing errors in the actual speed of said DC motor;

operating said CPU in accordance with a first set of instructions to modify said motor speed command signal by an amount tending to reduce rapidly changing detected speed errors; and

operating said CPU in accordance with a second set of instructions to modify said motor speed command signal by an amount tending to reduce detected slowly changing speed errors.

2. The method of claim 1 wherein said step of supplying signals representing the position or speed of said DC motor comprises generating successive index pulses as said motor moves past predetermined index positions, the freuqency and time separation of said index pulses being a function of the speed of said motor, and supplying said index pulses to said CPU;

and said step of operating said CPU to detect rapidly changing errors in the actual speed of said DC motor comprises determining from said index pulses an index time, storing a preceding index time, obtaining a difference time between the determined index time and the stored preceding index time, and calculating the DC motor speed error by subtracting a reference time value from the obtained difference time.

3. The method of claim 1 wherein said step of operating said CPU to modify said motor speed commmand signal to reduce slowly changing speed errors comprises combining a detected rapidly changing speed error with a reference speed value to produce the motor speed command signal;

determining when the number of detected rapidly changing speed errors in one direction exceeds the number of detected rapidly changing speed errors in the opposite direction by a predetermined amount; and

changing said reference speed value in a manner that reduces said detected rapidly changing speed errors in said one direction.

4. The method of claim 3 wherein said reference speed value is changed by a predetermined increment.

5. The method of claim 3, further including the step of limiting the value of the motor speed command signal produced by combining a detected rapidly changing speed error with a reference speed value to an amount greater than a predetermined minimum and less than a predetermined maximum.

6. The method of claim 1 wherein said motor speed command signal is a pulse width modulated (PWM) signal;

and wherein said step of operating said CPU to modify said motor speed command signal comprises modifying the duty cycle of said PWM signal.

7. The method of claim 6 wherein said step of converting said motor speed command signal to a motor drive signal comprises integrating said PWM signal to produce a DC signal.

8. The method of claim 1 wherein said motor speed command signal is a digital signal having a value representing a commanded motor speed;

said step of operating said CPU to modify said motor speed command signal comprises modifying the value of said digital signal; and

said step of converting said motor speed command signal to a motor drive signal comprises converting said digital signal to a corresponding DC analog signal.

9. The method of claim 1 wherein said step of selecting a respective phase of said DC motor to be energized comprises generating n successive commutating pulses as said DC motor moves through n successive positions;

and enabling a respective one of the n phases of said DC motor in accordance with said commutating pulses.

10. The method of claim 1 further comprising the steps of generating a signal representing the current actually flowing through the respective phases of said DC motor;

negatively feeding back the last-mentioned generated signal to said motor drive signal to produce a difference signal representing the difference between the motor drive signal and said last-mentioned generated signal; and

applying said difference signal to the selected phase.

11. The method of claim 10, further comprising the step of integrating said difference signal.

12. The method of claim 1 wherein said DC motor is a rotary motor;

and wherein said step of operating a CPU to generate a motor speed command signal includes a start-up routine of sensing whether successive signals representing the rotary position or speed of said DC motor have been supplied to said CPU within a predetermined time period;

sensing whether said DC motor has reached a predetermined speed within a preset number of revolutions thereof;

sensing whether said DC motor has maintained said predetermined speed for a predetermined number of revolutions; and

de-energizing said DC motor if any of the aforementioned occurrences have not been sensed.

13. The method of claim 12, further comprising the additional step of sensing if said DC motor has maintained said predetermined operating speed for a preset period of time and, if not, de-energizing said DC motor.

14. The method of claim 1 wherein n=2.

15. The method of claim 1 wherein n=3.

16. A method of driving an n-phase DC motor, where n>

1, comprising the steps of operating a central processing unit (CPU) to generate a motor speed command signal in accordance with a predetermined programmed set of instructions;

converting said motor speed command signal to a motor drive signal;

selecting a respective phase of said DC motor to be energized;

applying DC power to the selected phase as a function of said motor drive signal;

supplying to said CPU signals representing the position or speed of said DC motor;

operating said CPU to detect errors in the actual speed of said DC motor;

operating said CPU to modify said motor speed command signal by an amount tending to reduce detected speed errors; and

braking said DC motor when electrical power is interrupted, including storing a DC voltage level during the time period that power is applied, and using said stored DC voltage level to turn on phase selecting FET devices and shunt all of the n phases of said DC motor to a reference potential through said FET devices when said electrical power is interrupted.

17. Apparatus for controlling an n-phase DC motor comprising:

a programmed central processing unit (CPU) for generating a motor speed command signal;

converting means for converting said motor speed command signal to a motor drive signal;

switch means responsive to said motor drive signal for switching DC power to a respective phase of said DC motor;

index signal generating means for generating index signals as said DC motor operates and for supplying said index signals to said CPU;

said CPU being programmed to respond to said index signals for detecting both rapidly changing and slowly changing errors in the actual speed of said DC motor;

said CPU being programmed in accordance with a first set of instructions to modify said motor speed command signal by an amount that tends to reduce said radpily changing errors; and

said CPU being programmed in accordance with a second set of instructions to modify said motor speed command signal by an amount that tends to reduce said slowly changing errors.

18. The apparatus of claim 17 further comprising means for supplying respective commutating pulses to said switch means to select a corresponding phase of said DC motor for energization, whereby DC power is switched through said switch means to the selected phase in accordance with the value of the motor drive signal.

19. The apparatus of claim 18 wherein said commutating pulses are derived from said CPU.

20. The apparatus of claim 17 further comprising means for sensing the current flowing in said respective phases of said DC motor and for producing a feedback signal representative thereof;

difference means for producing a difference signal as a function of the difference between said motor drive signal and said feedback signal; and

means for applying said difference signal to said switch means, whereby said switch means responds to said applied difference signal for switching DC power to a respective phase of said DC motor.

21. The apparatus of claim 20 wherein said means for applying said difference signal to said switch means comprises an integrator.

22. The apparatus of claim 17 wherein n=2.

23. The apparatus of claim 17 wherein n=3.

24. The apparatus of claim 17 wherein said CPU generates a pulse width modulated (PWM) speed command signal, and said converting means comprises integrator means for producing a DC level as a function of the duty cycle of said PWM speed command signal.

25. The apparatus of claim 17 wherein said CPU generates a digital speed command signal having a value representing a commanded motor speed, and said converting means comprises a digital-to-analog converter for producing a DC level as a function of the value of said digital speed command signal.

26. The apparatus of claim 17 wherein said CPU is programmed to detect rapidly changing errors in the actual speed of said DC motor by determining the time interval between index signals, storing a representation of a preceding time interval between index signals, obtaining the difference between the determined time interval, and the preceding time interval, and calculating the rapidly changing DC motor speed error by subtracting a reference time interval from said difference.

27. The apparatus of claim 26 wherein said CPU is programmed to modify said speed command signal to reduce said slowly changing errors by combining the calculated rapidly changing DC motor speed error with a representation of a reference value to produce the speed command signal, determining when the number of detected rapidly changing speed errors in one direction exceeds the number of detected rapidly changing speed errors in the oppoiste direction by a predetermined amount, and changing said representation of said reference speed value to reduce said detected rapidly changing speed errors in said one direction.

28. The apparatus of claim 27 wherein said representation of said reference speed value is changed by a predetermined increment.

29. The apparatus of claim 27 wherein said CPU is programmed to limit the speed command signal to an amount greater than a predetermined minimum value and less than a predetermined maximum value.

30. The apparatus of claim 17 wherein said DC motor is a rotary motor;

and wherein said CPU is programmed to control said DC motor during an initial start-up mode by sensing whether successive index signals have been generated within a predetermined time, sensing whether said DC motor has reached a predetermined operating speed within a preset number of revolutions thereof, sensing whether said predetermined operating speed has been maintained for a predetermined number of revolutions, and terminating said motor speed command signal if any of the aforementioned occurrences has not been sensed.

31. The apparatus of claim 30 wherein said CPU is further programmed to sense during said initial start-up mode if said predetermined operating speed has been maintained for a preset period of time and, if not, to terminate said motor speed command signal.

32. Apparatus for controlling an n-phase DC motor comprising:

a programmed central processing unit (CPU) for generating a motor speed command signal;

converting means for converting said motor speed command signal to a motor drive signal;

switch means responsive to said motor drive signal for switching DC power to a respective phase of said DC motor;

index signal generating means for generating index signals as said DC motor operates and for supplying said index signal to said CPU;

said CPU being programmed to respond to said index signals for detecting errors in the actual speed of said DC motor and to modify said motor speed command signal by an amount that tends to reduce said errors;

means for supplying respective commutating pulses to said switch means to select a corresponding phase of said DC motor for energization, whereby DC power is switched through said switch means to the selected phase in accordance with the value of the motor drive signal; and

wherein said switch means comprises n FET devices and a bipolar transistor, said FET devices being connected in common with said bipolar transistor, each FET device being connected to a respective phase of said DC motor and being rendered conductive by a respective commutating pulse, and said bipolar transistor being responsive to said motor drive signal to thereby determine the current that flows through the conductive FET device and a respective phase.

33. The apparatus of claim 32 further comprising energizable power supply means for supplying operating potential to said apparatus;

storage means for storing a voltage when said power supply means is energized; and

means responsive to the de-energization of said power supply means to apply said stored voltage to said n FET devices for rendering said n FET devices conductive and thereby short circuit the n phases of said DC motor to brake said motor.