Digital slicer having a pulse-width locked loop

• US 4,622,586 A
• Filed: 04/04/1985
• Issued: 11/11/1986
• Est. Priority Date: 04/04/1985
• Status: Expired due to Fees

• Current Assignee: RCA Corporation
• Original Assignee: RCA Corporation
• Inventors: Megeid, Mohamed M. A.
• Primary Examiner(s): NG, JIN FAY
• Application Number:
  US06/719,803
• Time in Patent Office: 586 Days
• Field of Search: 358/150, 358/153, 358/158.19, 328/139, 328/164, 329/106, 307/231, 307/234, 307/527, 375/111, 375/113, 370/77, 455/608
• US Class Current: 348/532
• CPC Class Codes: H03K 5/082 with an adaptive threshold
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A bit-decision circuit or slicer for a digital communications receiver includes a first comparator which compares the received signal level with a reference slicing level. In order to have the lowest error rate, the reference slicing level must be controlled. Control is provided by periodic level indicating pulses in the transmitted signal. The level indicating pulses have predetermined nominal duration and controlled rise and fall times. A pulse width locked loop at the receiver responds to the level indicating pulse at the output of the comparator. The pulse width locked loop includes a start-stop oscillator which produces an odd or an even number of oscillations in response to each level-indicating pulse depending upon the ON time of the oscillator. A flip-flop coupled to the oscillator changes state during each oscillation, so that an even number of oscillations causes the flip-flop output to remain in the same state after the level indicating pulse as before, while an odd number of oscillations causes a change of state. The average D.C. level at the output of the flip-flop therefore changes significantly for a change of duration of the level indicating pulse corresponding to one clock oscillation cycle or a portion of a clock oscillator cycle. The flip-flop output level is filtered and applied as an input signal to a second comparator. The second comparator switches state in response to excursion of the filtered flip-flop signal above and below a reference level. The output of the second comparator is filtered to form the reference slicing level for the first comparator. This closes a pulse width locked loop which takes excursions between two extreme values of pulse width. The data pulses occurring in the interval between level indicating pulses are compared with the same reference level for low error rate.

Claims

1. An adaptive slicer for a bit stream, which bit stream includes level indicating pulses having a predetermined nominal duration and finite rise and fall times, the slicer comprising:

controllable comparator means including a first input terminal and a second input terminal, said first input terminal being coupled for receiving said bit stream and for comparing the instantaneous amplitude of said bit stream with a reference slicing level signal applied to said second input terminal for generating bilevel signals representing bit decisions, the duration of said bilevel signals during said level indicating pulse being indicative of the instantaneous slicing level;

pulse separating means coupled to said controllable comparator means for separating said level indicative pulse portion of said bilevel signals from the remainder of said bit stream to produce a separated level indicating pulse;

controllable start-stop oscillator means coupled to said pulse separating means and responsive to said separated level indicating pulse for generating oscillations at a rate such that a plurality of cycles of said oscillations occur during an interval equal to said nominal duration;

bistable means coupled to said controllable start-stop oscillator means and responsive to each cycle of said oscillations for changing state to form an umprocessed raw control signal, said unprocessed control signal having a first state prior to receipt of each level indicating pulse, and having said first state after receipt of said level indicating pulse if said controllable start-stop oscillator means produces an even number of said cycles of said oscillations in response to said separated level indicating pulse, and having a second state after receipt of said level indicating pulse if said controllable start-stop oscillator means produces an odd number of said cycles of said oscillations in response to said separated level indicating pulse, whereby the average level of said unprocessed control signal varies in the interval between said level indicating pulses depending upon the slicing level;

first filter means coupled to said bistable means for receiving said unprocessed control signal therefrom for filtering said unprocessed control signal to produce a first control signal;

second comparator means coupled to said first filter means for comparing said first control signal with a predetermined reference level to generate a bilevel compared output signal which changes state when said first control signal passes through a value corresponding to said predetermined reference level;

second filter means coupled to said second comparator means and to said second input terminal of said controllable comparator means for filtering said bilevel compared output signal to form said reference slicing level, and for applying said reference slicing level to said second input terminal of said controllable comparator means to form a pulse width locked control loop for maintaining said slicing level near a predetermined value.

2. An adaptive slicer according to claim 1 wherein said controllable start-stop oscillator means comprises:

a NOR gate including first and second input terminals and also including an output terminal;

transmission-line means coupled between said first input terminal and said output terminal, said transmission-line means having a predetermined delay; and

coupling means coupled to said pulse separating means and to said second input terminal of said NOR gate for coupling said separated level indicating pulse to said second input terminal of said NOR gate whereby a logic HIGH level of said separated level indicating pulse causes said oscillations at a rate controlled by said delay.

3. A slicer according to claim 1 wherein said bistable means comprises a D-type flip-flop.

4. A slicer according to claim 1 wherein each of said first and second filter means comprises series-coupled resistance means and shunt-coupled capacitance means.

5. An adaptive slicer for a bit stream, which bit stream includes recurrent sync information and level indicating pulses having a predetermined nominal duration and finite rise and fall times, the slicer comprising:

controllable comparator means including a first input terminal and a second input terminal, said first input terminal being coupled for receiving said bit stream and for comparing the instantaneous amplitude of said bit stream with a reference slicing level signal applied to said second input terminal for generating inverted and noninverted bilevel signals representing bit decisions, the duration of at least one of said inverted and noninverted bilevel signals during said level indicating pulse being indicative of the instantaneous slicing level;

sync separating means coupled to said controllable comparator means for separating said sync information from one of said inverted and noninverted bilevel signals from the remainder of said bit stream to produce a generated sync pulse;

pulse generating means coupled to said sync separating means for generating a window pulse having a predetermined duration in response to an edge of said generated pulse;

coincidence means including a first input terminal coupled to said pulse generating means for receiving said window pulse and also including a second input terminal coupled to said controllable comparator means for receiving one of said inverted and noninverted bilevel signals for generating a bilevel coincidence signal in response to said level indicating pulses;

controllable start-stop oscillator means coupled to said coincidence means and responsive to one level of said bilevel coincidence signal for generating oscillations at a rate such that a plurality of cycles of said oscillations occur during an interval equal to said nominal duration;

bistable means coupled to said controllable start-stop oscillator means and responsive to each cycle of said oscillations for changing state to form a raw control signal, said raw control signal having a first state prior to receipt of each level indicating pulse, and having said first state after receipt of said level indicating pulse if said controllable start-stop oscillator means produces an even number of said cycles of said oscillations in response to said separated level indicating pulse, and having a second state after receipt of said level indicating pulse if said controllable start-stop oscillator means produces an odd number of said cycles of said oscillations in response to said separated level indicating pulse, whereby the average level of said raw control signal varies in the interval between said level indicating pulses depending upon the slicing level;

first filter means coupled to said bistable means for receiving said raw control signal therefrom for filtering said raw control signal to produce a first control signal;

second comparator means coupled to said first filter means for comparing said first control signal with a predetermined reference level to generate a bilevel compared output signal which changes state when said first control signal passes through a value corresponding to said predetermined reference level;

second filter means coupled to said second comparator means and to said second input terminal of said controllable comparator means for filtering said bilevel compared output signal to form said reference slicing level, and for applying said reference slicing level to said second input terminal of said controllable comparator means to form a pulse width locked control loop for maintaining said slicing level near a predetermined value.

6. An adaptive slicer according to claim 5 wherein said controllable start-stop oscillator means comprises:

a NOR gate including first and second input terminals and also including an output terminal;

transmission-line means coupled between said first input terminal and said output terminal, said transmission-line means having a predetermined delay; and

coupling means coupled to said pulse separating means and to said second input terminal of said NOR gate for coupling said separated level indicating pulse to said second input terminal of said NOR gate whereby a logic HIGH level of said separated level indicating pulse causes said oscillations at a rate controlled by said delay.

7. A slicer according to claim 5 wherein said bistable means comprises a D-type flip-flop.

8. A slicer according to claim 5 wherein each of said first and second filter means comprises series-coupled resistance means and shunt-coupled capacitance means.

9. A slicer according to claim 5 wherein said sync separating means comprises a correlator responsive to a predetermined bit pattern of said sync information.

10. A slicer according to claim 9 wherein said correlator comprises:

bit clock regeneration means coupled to said controllable comparator means for regenerating bit carrier from said bilevel signals;

shift register means coupled to said controllable comparator means and to said bit clock regenerating means for storing and shifting said bilevel signals for a predetermined number of clock cycles, and for making at least some of the resulting stored and shifted bilevel signals available at parallel output terminals;

a source of said predetermined bit pattern; and

comparison means coupled to said parallel output terminals of said shift register means and to said source of said predetermined bit pattern for comparing said stored and shifted bilevel signals with said predetermined bit pattern and for generating said generated sync pulse.

11. A binary communications arrangement, comprising:

a source of binary information;

a source of level indicating pulses having rise and fall times which remain constant;

multiplexing and transmitting means coupled to said source of binary information and to said source of level indicating pulse for multiplexing said binary information together with said level indicating pulses to form a transmitted signal;

first comparator means coupled to said multiplexing and transmitting means for comparing said transmitted signal with a controllable reference voltage for generating compared pulses including compared level indicating pulses;

gated oscillator means coupled to said first comparator means for generating bursts of oscillations in response to said compared level indicating pulses;

bistable means coupled to said gated oscillator means for changing state in response to each of said oscillations in said bursts of oscillations, said bistable means producing an output signal having a first state before receipt by said gated oscillator means of said compared level indicating pulses and having a second state after receipt by said gated comparator means of said compared level indicating pulse if the duration of said compared level indicating pulse substantially corresponds to the duration of an odd number of said oscillations, and having said first state after receipt by said gated comparator means of said compared level indicating pulse if the duration of said compared level indicating pulse substantially corresponds to the duration of an even number of said oscillations;

first filter means coupled to said bistable means for filtering said output signal of said bistable means for producing a first averaged signal;

second comparator means coupled to said first filter means for comparing said first averaged signal with a reference voltage having a value intermediate the voltages represented by said first and second states of said output signal of said bistable means for generating an unfiltered control signal; and

second filter means coupled to said first comparator means and to said second comparator means for filtering said unfiltered control signal to generate said controllable reference voltage, whereby the duration of said compared pulses is held substantially constant.

12. An arrangement according to claim 11 wherein said multiplexing and transmitting means comprises an optical transmitter, an optical transmission path and an optical receiver, said optical receiver being coupled to the input of said first comparator means.

13. An arrangement according to claim 11 wherein said bistable means comprises a D-type flip-flop having its data input terminal coupled to its Q output terminal, its clock input terminal coupled to said gated oscillator for receiving said bursts of oscillations therefrom for producing said output signal at its Q output terminal.

14. An arrangement according to claim 11 wherein said gated oscillator means comprises:

bit clock regeneration means coupled to said first comparator means for regenerating bit carrier from said transmitted signal;

shift register means coupled to said first comparator means and to said bit clock regenerating means for storing and shifting said compared pulses and for making at least some of the resulting stored and shifted compared pulses available at parallel output terminals;

a source of predetermined bit pattern;

gating pulse generating means coupled to said source of predetermined bit pattern and to said shift register means for generating a level indicating pulse gating signal in response to a predetermined pattern of said stored and shifted compared pulses;

gating means coupled to said first comparator means and to said gating pulse generating means for gating compared pulses representative of said level indicating pulses; and

start-stop oscillator means coupled to said gating means for generating said bursts of oscillations in response to said compared pulses representative of said level indicating pulses.

15. A digital slicer for a bit stream, said bit stream including level indicating pulses, said slicer comprising:

comparator means including first and second input terminals, said first input terminal being coupled for receiving said bit stream and said second input terminal being coupled for receiving a reference slicing signal, for comparing said bit stream with said reference slicing signal for generating compared pulses including compared level indicating pulses;

gated oscillator means coupled to said comparator means for generating bursts of oscillations in response to said compared level indicating pulses;

bistable means coupled to said gated oscillator means for changing state in response to each of said oscillations in said bursts of oscillations, said bistable means producing an output signal having a first state before receipt of each of said bursts of oscillators and having a second state after receipt of one of said bursts of oscillations containing an odd number of oscillations and having said first state after receipt of one of said bursts of oscillations containing an even number of oscillations;

averaging and control signal processing means coupled to said bistable means for averaging said first and second states of said output signal of said bistable means and for processing the signal so averaged to generate said reference slicing level; and

coupling means coupled to said averaging and control signal processing means and to said comparator means for coupling said reference slicing level to said comparator means with a polarity selected to maintain constant duration of said compared level indicating pulses.

16. A slicer according to claim 15 wherein said averaging and control signal processing means comprises:

first filter means coupled to said bistable means for averaging said output signal of said bistable means to produce a filtered control signal;

second comparator means coupled to said first filter means for comparing said filtered control signal with a reference signal for generating a second bilevel signal; and

second filter means coupled to said second comparator means for averaging said second bilevel signal to produce said reference slicing level.

17. A slicer according to claim 15 wherein said gated oscillator means comprises:

correlator means coupled to said comparator means for generating timing pulses having a particular timing relation with said level indicating pulses;

gating window pulse generating means coupled to said correlator means for generating a gating window pulse in response to each said timing pulse;

gating means coupled to said comparator and to said gating window pulse generating means for gating each said level indicating pulse to an output terminal; and

start-stop oscillator means coupled to said gating means for generating said bursts of oscillations in response to each said level indicating pulse.

18. A slicer according to claim 15, said slicer further including a starting circuit, comprising:

start signal generating means coupled to said first input terminal of said comparator means for averaging said bit stream to produce a start signal approximating said slicing level;

level indicating pulse separation indicating means coupled to said gated oscillator means for generating a start enable signal indicating lack of said compared level indicating pulses; and

start signal gating means coupled to said start signal generating means and to said level indicating pulse separation indicating means for gating said start signal to said coupling means for application of said start signal to said comparator means to aid in starting.

19. A slicer according to claim 15 wherein said bit stream represent a television signal which includes a television synchronizing signal having a unique bit pattern.

20. A slicer according to claim 19 further comprising:

synchronizing signal identifying means including a memory for storing a bit pattern corresponding to said unique bit pattern, a clocked store coupled to said comparator for storing successive bits, and correlator means coupled to said clocked store and to said memory for comparing bits of said clocked store with bits of said memory for generating a signal representing arrival of said synchronizing signal.