Microprocessor reset system
First Claim
1. A microprocessor reset system comprising:
- a microprocessor having a reset input terminal,an information line coupled to said microprocessor on which said microprocessor will transmit information data, andreset means coupled between said information line and said microprocessor reset terminal for providing a reset pulse to said microprocessor in response to an initial predetermined signal transition on said information line which is preceded by the existence of a predetermined voltage level which exists for a predetermined minimum duration of time, said reset circuit effectively ignoring subsequent substantially identical signal transitions which occur on said information line during said transmission of information data unless they are directly preceded by the existence of said predetermined voltage level which exists for at least said minimum duration of time.
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Accused Products
Abstract
A wireless telephone communication system 10 is provided in which a portable unit 12 communicates with a base unit 11 over a wireless (radio) communication link 15. Access to a telephone network 15b by the portable unit 12, via the base unit 11, is permitted when the base and portable units have corresponding ID codes stored therein. The base ID code is hardwired into the base unit 11, and the portable unit 12 learns its ID code from the base unit in response to mechanically coupling the base and portable units together via plug and socket assemblies 28 and 45. The base and portable units each have associated microprocessors 22 and 40 which implement the transfer of an ID code to the portable unit from the base unit via conductors (24'"'"'-42'"'"') which are part of the plug and socket assemblies. The plug and socket assemblies, when mated, also provide a connection between a battery charging supply circuit 25 in the base and a battery 46 in the portable. Reset circuits 29 and 50 are provided in the base and portable units and control the resetting of the microprocessors 22 and 40.
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Citations
14 Claims
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1. A microprocessor reset system comprising:
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a microprocessor having a reset input terminal, an information line coupled to said microprocessor on which said microprocessor will transmit information data, and reset means coupled between said information line and said microprocessor reset terminal for providing a reset pulse to said microprocessor in response to an initial predetermined signal transition on said information line which is preceded by the existence of a predetermined voltage level which exists for a predetermined minimum duration of time, said reset circuit effectively ignoring subsequent substantially identical signal transitions which occur on said information line during said transmission of information data unless they are directly preceded by the existence of said predetermined voltage level which exists for at least said minimum duration of time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification