Apparatus for interfacing between at least one channel and at least one bus
First Claim
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1. Interface apparatus for a multichannel system for interfacing between at least one asynchronous bus and a selectable one of the channels, each bus having an identical protocol which permits communication between a bus and only one channel at a time, the protocol further defining legal and illegal message signal characteristics stored in each channel, said signals formatted as words of a specified number of bits in messages having a specified maximum number of words, each channel'"'"'s portion of said interface apparatus comprising:
- message validation means, responsive to incoming signals to the channel from an asynchronous bus and responsive to outgoing signals from the channel for transmittal on said bus, for comparing said incoming signals from said bus to stored legal and illegal signal characteristics and providing, in response to a comparison finding an illegal incoming signal characteristic, for interface apparatus interfacing with only one asynchronous bus a channel sever signal, and for similarly providing a channel select signal in response to said comparison for interface apparatus interfacing with more than one asynchronous bus, said validation means comparing said outgoing signals to legal and illegal signal characteristics and providing a channel sever signal in response to a comparison finding an illegal outgoing signal characteristic;
switching circuitry, responsive to incoming signals to the channel from a selected one of a selected number of the asynchronous busses and responsive to outgoing signals from the channel to said selected asynchronous bus, for providing selectable signal paths between the channel and at least one asynchronous bus in response to said channel select signal and for severing the signal path between the channel and any and all other selectable asychronous busses in response to said channel sever signal;
a bus interface circuit, responsive to incoming signals from said selected asynchronous bus and responsive to outgoing signals from the channel to said bus, for efficiently packing and coherently transferring validated incoming and outgoing signals between the channel and said asynchronous bus;
local RAM, responsive to coherent incoming signals for storing said coherent incoming signals in packed form;
an independent interchannel communication link, responsive to said coherent signals stored in each channel'"'"'s local RAM for synchronously transmitting said signals in packed form to other channels;
link RAM, responsive to said packed signals transferred from another channel on said interchannel link for storing said transferred packed signals; and
signal processor means, responsive to incoming signals processed by said bus interface circuit for providing packed messages having end of data identification tags for storage in a preselected area of said local RAM and for transmission to and unpacking by other channels via said interchannel link and for storing messages received from other channels via said interchannel link in said link RAM.
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Abstract
A coherent interface between one or more asynchronous busses and one or more channels in which only one channel is permitted to communicate with a bus at a time is disclosed.
34 Citations
5 Claims
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1. Interface apparatus for a multichannel system for interfacing between at least one asynchronous bus and a selectable one of the channels, each bus having an identical protocol which permits communication between a bus and only one channel at a time, the protocol further defining legal and illegal message signal characteristics stored in each channel, said signals formatted as words of a specified number of bits in messages having a specified maximum number of words, each channel'"'"'s portion of said interface apparatus comprising:
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message validation means, responsive to incoming signals to the channel from an asynchronous bus and responsive to outgoing signals from the channel for transmittal on said bus, for comparing said incoming signals from said bus to stored legal and illegal signal characteristics and providing, in response to a comparison finding an illegal incoming signal characteristic, for interface apparatus interfacing with only one asynchronous bus a channel sever signal, and for similarly providing a channel select signal in response to said comparison for interface apparatus interfacing with more than one asynchronous bus, said validation means comparing said outgoing signals to legal and illegal signal characteristics and providing a channel sever signal in response to a comparison finding an illegal outgoing signal characteristic; switching circuitry, responsive to incoming signals to the channel from a selected one of a selected number of the asynchronous busses and responsive to outgoing signals from the channel to said selected asynchronous bus, for providing selectable signal paths between the channel and at least one asynchronous bus in response to said channel select signal and for severing the signal path between the channel and any and all other selectable asychronous busses in response to said channel sever signal; a bus interface circuit, responsive to incoming signals from said selected asynchronous bus and responsive to outgoing signals from the channel to said bus, for efficiently packing and coherently transferring validated incoming and outgoing signals between the channel and said asynchronous bus; local RAM, responsive to coherent incoming signals for storing said coherent incoming signals in packed form; an independent interchannel communication link, responsive to said coherent signals stored in each channel'"'"'s local RAM for synchronously transmitting said signals in packed form to other channels; link RAM, responsive to said packed signals transferred from another channel on said interchannel link for storing said transferred packed signals; and signal processor means, responsive to incoming signals processed by said bus interface circuit for providing packed messages having end of data identification tags for storage in a preselected area of said local RAM and for transmission to and unpacking by other channels via said interchannel link and for storing messages received from other channels via said interchannel link in said link RAM. - View Dependent Claims (2, 3, 4)
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5. Interface apparatus for a multi-asynchronous bus system for interfacing between at least one channel and a selectable one of the asynchronous busses, each bus having an identical protocol which permits communication between a bus and only one channel at a time, the protocol further defining legal and illegal message signal characteristics stored in each channel, said signals formatted as words of a specified number of bits in messages having a specified maximum number of words, each channel'"'"'s portion of said interface apparatus comprising:
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message validation means, responsive to incoming signals to the channel from an asynchronous bus and responsive to outgoing signals from the channel for transmittal on said bus, for comparing said incoming signals from said bus to stored legal and illegal signal characteristics and providing, in response to a comparision finding an illegal incoming signal characteristic a bus select signal in response to said comparision, said validation means comparing said outgoing signals to legal and illegal signal characteristics and providing a channel sever signal in response to a comparision finding an illegal outgoing signal characteristic; switching circuitry, responsive to incoming signals to the channel from a selected one of the asynchronous busses and responsive to outgoing signals from the channel to said selected asynchronous bus, for providing selectable signal paths between the channel and at least one asynchronous bus in response to said bus select signal and for severing the signal path between the channel and any and all other selectable asynchronous busses in response to said channel sever signal; a bus interface circuit, responsive to incoming signals from said selected asynchronous bus and responsive to outgoing signal from the channel to said bus, for efficiently packing and coherently transferring validated incoming and outgoing signals between the channel and said bus; local RAM, responsive to coherent incoming signal for storing said coherent incoming signals in packed form; an independent interchannel communication link, responsive to said coherent signals stored in each channel'"'"'s local RAM for synchronously transmitting said signal in packed form to other channels; link RAM, responsive to said packed signals transferred from another channel on said interchannel link for storing said transferred packed signals; and signal processor means, responsive to incoming signals processed by said bus interface circuit for providing packed messages each having an end of data identification tag for storage in said local RAM and for transmission to and unpacking by other channels via said interchannel link and for storing messages received from other channels via said interchannel link in said link RAM.
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Specification