All digital IDMA dynamic channel allocated satellite communications system and method

• US 4,625,308 A
• Filed: 11/30/1982
• Issued: 11/25/1986
• Est. Priority Date: 11/30/1982
• Status: Expired due to Fees

• Current Assignee: Gilat Satellite Networks Limited
• Original Assignee: American Satellite Company
• Inventors: Andrews, Bruce S., Eiserike, Steven S., Tisdale, William R. H., Kolodgie, Kathleen J., Kim, Kap S., Nash, T. Randolph
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Scutch, III, Frank M.
• Application Number:
  US06/445,501
• Time in Patent Office: 1,456 Days
• Field of Search: 370/104, 370/95, 370/91, 370/85
• US Class Current: 370/321
• CPC Class Codes: H04B 7/2123 Variable assignment, e.g. demand assignment

Abstract

An all digital TDMA dynamic channel allocated satellite communications system and method provides a satellite communications network between geographically separated nodes. The topology of the network is controlled by an on-line master node in accordance with user demands and operator commands received from the nodes in the network. A frame communication format is employed where each node in the system is allocated a burst within each frame. The length of the bursts is controlled by the on-line master node to provide the communications channels in the network. Control information to and from the on-line master node is conveyed in the network via the satellite link in selected frame bursts. In this way, the on-line master node dynamically controls the topology of the satellite communications network.

Claims

1. A communication system, comprising:

(a) transmission means for transmitting a radio frequency signal in accordance with a first IF signal, and for providing a second IF signal in accordance with a received radio frequency signal;

(b) time division multiple access means for generating said first IF signal by assembling frames of first serial data, and for providing second serial data by disassembling said second IF signal;

(c) switch multiplexer means for supplying said first serial data from stored first parallel data under control of first control signals, and for providing second parallel data from said second serial data under control of second control signals;

(d) bus extension means for providing said stored first parallel data by storing first parallel data, and for providing stored second parallel data by storing said second parallel data;

(e) digital input/output means for supplying said first parallel data in accordance with first digital data, and for supplying second digital data in accordance with said stored second parallel data;

(f) conversion means for providing said first digital data in accordance with first analog signals, and for providing second analog signals in accordance with said second digital data; and

(g) control means for providing said first and second control signals in accordance with input signals and a stored program.

2. A communications system, for use with a satellite, comprising a plurality of nodes, each of said nodes comprising:

(a) transmission means for transmitting a first radio frequency signal to the satellite in accordance wih a first IF signal, and for providing a second IF signal in accordance with a second radio frequency signal received from the satellite;

(b) TDMA means, coupled to said transmission means, for generating said first IF signal by providing bursts of first serial data, and for providing second serial data by disassembling said second IF signal;

(c) first bit map means for storing first routing data;

(d) second bit map means for storing second routing data;

(e) routing means, coupled to said TDMA means and to said first bit map means, for supplying said first serial data from first parallel data in accordance with said first routing data, and, coupled to said TDMA means and to said second bit map means, for providing second parallel data from said second serial data in accordance with said second routing data;

(f) a plurality of first interfaces and a plurality of second interfaces; and

(g) first bus means, coupled to said routing means and to said plurality of first interfaces, for providing said first parallel data from said plurality of first interfaces, and, coupled to said routing means and to said plurality of second interfaces, for providing said second parallel data to said plurality of second interfaces.

3. The communications system as recited in claim 2, further comprising:

control means, coupled to said first bit map means, for modifying said first routing data in accordance with first control data, and, coupled to said second bit map means, for modifying said second routing data in accordance with second control data.

4. The communications system as recited in claim 3, wherein said control means further comprises:

first connectivity map means for storing first connectivity map data;

first means, coupled to said first connectivity map means, for supplying said first control data in accordance with said first connectivity map data;

second connectivity map means for storing second connectivity map data; and

second means, coupled to said second connectivity map means, for supplying said second control data in accordance with said second connectivity map data.

5. The communications system as recited in claim 4, wherein said first means comprises:

storage means for storing a program; and

processor means, coupled to said storage means and to said first connectivity map means, for producing said first control data in accordance with said stored program and said first connectivity map data.

6. The communications system as recited in claim 4, wherein said second means comprises:

storage means for storing a program; and

processor means, coupled to said storage means and to said second connectivity map means, for producing said second control data in accordance with said stored program and said connectivity map data.

7. The communications system as recited in claim 4, wherein said control means further comprises:

third means, coupled to said routing means, for providing said first connectivity map data in accordance with some of said second serial data.

8. The communications system, as recited in claim 4, wherein said control means further comprises:

third means, coupled to said routing means, for providing said second connectivity map data in accordance with some of said second serial data.

9. The communications system, as recited in claim 2, wherein said first bit map means comprises:

active means for storing said first routing data; and

inactive means for storing updated first routing data.

10. The communications system as recited in claim 9, further comprising:

control means, coupled to said first bit map means, for supplying said updated first routing data in accordance with control data.

11. The communications system as recited in claim 10, wherein said control means comprises:

connectivity map means for storing connectivity map data; and

first means, coupled to said connectivity map means, for supplying said control data in accordance with said connectivity map data.

12. The communications system as recited in claim 11, wherein said control means further comprises:

second means, coupled to said routing means, for providing said connectivity map data in accordance with some of said second serial data.

13. The communications system as recited in claim 12, wherein said routing means further comprises:

switch means, coupled to said control means, for replacing said first routing data with said updated first routing data in accordance with some of said second serial data.

14. The communications system as recited in claim 2, wherein said second bit map means comprises:

active means for storing said second routing data; and

inactive means for storing updated second routing data.

15. The communications system as recited in claim 14, further comprising:

control means, coupled to said second bit map means, for supplying said updated second routing data in accordance with control data.

16. The communications system as recited in claim 15, wherein said control means comprises:

connectivity map means for storing connectivity map data; and

first means, coupled to said connectivity map means, for supplying said control data in accordance with said connectivity map data.

17. The communications system as recited in claim 16, wherein said control means further comprises:

second means, coupled to said routing means, for providing said connectivity map data in accordance with some of said second serial data.

18. The communications system as recited in claim 17, wherein said routing means further comprises:

switch means, coupled to said control means, for replacing said second routing data with said updated second routing data in accordance with some of said second serial data.

19. The communications system as recited in claim 2, wherein said first bit map means comprises:

a plurality of entry means for storing associated channel addresses and word numbers, each of said channel addresses indicative of one of said plurality of first interfaces, and each of said word numbers indicative of the number of data words of said first parallel data from said one of said plurality of first interfaces.

20. The communications system as recited in claim 2, wherein said second bit map means comprises:

a plurality of entry means for storing associated channel addresses and word numbers, each of said channel addresses indicative of one of said plurality of second interfaces, and each of said word numbers indicative of the number of data words of said second parallel data provided to said one of said plurality of second interfaces.

21. The communications system as recited in claim 19, wherein said routing means comprises:

word counter means for counting the number of data words of said first parallel data; and

event counter means for selecting one of said plurality of entry means in accordance with said number of data words counted by said word counter means.

22. The communications system as recited in claim 21, wherein said routing means further comprises:

comparator means, coupled to said word counter means and to said first bit map means, for incrementing said event counter means when the number of data words counted by said word counter means corresponds to said word number contained in said entry means selected by said event counter means.

23. The communications system as recited in claim 20, wherein said routing means comprises:

word counter means for counting the number of data words of said second serial data; and

event counter means for selecting one of said plurality of entry means in accordance with said number of data words counted by said word counter means.

24. The communications system as recited in claim 23, wherein said routing means further comprises,

comparator means, coupled to said word counter means and to said second bit map means, for incrementing said event counter means when the number of data words counted by said word counter corresponds to said word number contained in said entry means selected by said event counter means.

25. The communications system as recited in claim 21, wherein said TDMA means comprises:

means for sensing said bursts of first serial data to detect the beginning of a frame.

26. The communications system as recited in claim 25, wherein said routing means further comprises:

resetting means, coupled to said means for sensing said bursts of first serial data, for resetting said word counter means and said event counter means when the beginning of a frame is detected.

27. The communications system as recited in claim 23, wherein said TDMA means comprises:

means for sensing said bursts of second serial data to detect the beginning of a frame.

28. The communications system as recited in claim 27, wherein said routing means further comprises:

resetting means, coupled to said means for sensing said bursts of second serial data, for resetting said word counter means and said event counter means when the beginning of a frame is detected.

29. The communications system as recited in claim 2, wherein said routing means comprises:

transmit controller means for providing said first serial data from said first parallel data.

30. The communications system as recited in claim 29, wherein said transmit controller means comprises,

register means for converting said first parallel data to said first serial data.

31. The communications system as recited in claim 2, wherein said routing means comprises:

receive controller means for providing said second parallel data from said second serial data.

32. The communications system as recited in claim 31, wherein said receive controller means comprises:

register means for converting said second serial data to said second parallel data.

33. The communications system as recited in claim 2, wherein said TDMA means comprises:

first means for sensing said bursts of first serial data to detect the beginning of a transmit frame; and

second means for sensing said second serial data to detect the beginning of a receive frame.

34. The communications system as recited in claim 33, wherein said routing means comprises:

third means, coupled to said first means, for generating first timing data in response to the detection of the beginning of said transmit frame; and

fourth means, coupled to said second means, for generating second timing data in response to the detection of the beginning of said receive frame.

35. The communications system as recited in claim 3, further comprising:

interface means, coupled to said routing means and to said first bit map means, for supplying said first control data in accordance with some of said second serial data.

36. The communications system as recited in claim 35, wherein said interface means comprises:

buffer means, coupled to said routing means and to said first bit map means, for buffering some of said second serial data to produce said first control data; and

sequencer means, coupled to said routing means and to said buffer means, for controlling said buffering by said buffer means in accordance with some of said second serial data.

37. The communications system as recited in claim 2, further comprising:

second bus means coupled to said first bit map means and to said plurality of first interfaces; and

control means, coupled to said first bus means and to said second bus means, for supplying first control data via said second bus means to said first bit map means to modify said first routing data in accordance with some of said second serial data received via said first bus means from said routing means.

38. The communications system as recited in claim 37, further comprising:

means, coupled to said first bus means and to said second bus means, for controlling the providing of said first parallel data from said plurality of first interfaces via said first bus means to said routing means in accordance with said first routing data provided via said second bus means.

39. The communications system as recited in claim 37, wherein said control means further comprises:

buffer means, coupled to said first bus means and to said second bus means, for providing to said second bus means said first control data by buffering some of said second serial data; and

sequencer means for controlling said buffering by said buffer means.

40. The communications system as recited in claim 39, wherein said control means further comprises:

storage means for storing a program; and

processor means, coupled to said storage means, to said first bus means, and to said sequencer means, for controlling said sequencer means in accordance with said program and some of said second serial data.

41. The communications system as recited in claim 3, further comprising:

interface means, coupled to routing means and to said second bit map means, for supplying said second control data in accordance with some of said second serial data.

42. The communications system as recited in claim 41, wherein said interface means comprises:

buffer means, coupled to said routing means and to said second bit map means, for buffering some of said second serial data to produce said second control data; and

sequencer means, coupled to said routing means and to said buffer means, for controlling said buffering by said buffer means in accordance with some of said second serial data.

43. The communications system as recited in claim 2, further comprising:

second bus means coupled to said second bit map means and to said plurality of second interfaces; and

control means, coupled to said first bus means and to said second bus means, for supplying first control data via said second bus means to said second bit map means to modify said second routing data in accordance with some of said second serial data received via said first bus means from said routing means.

44. The communications system as recited in claim 43, further comprising:

means, coupled to said first bus means and to said second bus means, for controlling the providing of said second parallel data to said plurality of second interfaces via said first bus means from said routing means in accordance with said first routing data provided via said second bus means.

45. The communications system as recited in claim 43, wherein said control means further comprises:

buffer means, coupled to said first bus means and to said second bus means, for providing said second control data by buffering some of said second serial data; and

sequencer means for controlling said buffering by said buffer means.

46. The communications system as recited in claim 45, wherein said control means further comprises:

storage means for storing a program; and

processor means, coupled to said storage means, to said first bus means, and to said sequencer means, for controlling said sequencer means in accordance with said program and some of said second serial data.

47. The communications system as recited in claim 37, wherein said control means further comprises:

control interface means, coupled to said first bus means, for providing some of said first parallel data in accordance with said first routing data.

48. The communications system as recited in claim 47, wherein said control interface means comprises:

buffer means, coupled to said first bus means, for providing some of said first parallel data; and

sequencer means, coupled to said second bus means and to said buffer means, for controlling the providing of some of said first parallel data in accordance with said first routing data.

49. The communications system as recited in claim 48, wherein said sequencer means comprises:

memory means for storing sequencing data; and

counter means, coupled to said memory means, for addressing said buffer means in accordance with said sequencing data.

50. The communications system as recited in claim 49, wherein said control interface means further comprises:

comparator means, coupled to said second bus, for accessing said memory means to provide said sequencing data to said counter means in accordance with said first routing data.

51. The communications system as recited in claim 43, wherein said control means further comprises:

control interface means, coupled to said first bus means, for receiving some of said second parallel data in accordance with second routing data.

52. The communications system as recited in claim 51, wherein said control interface means comprises,

buffer means, coupled to said first bus means, for receiving some of said second parallel data;

and

sequencer means, coupled to said second bus means and to said buffer means, for controlling the receiving of some of said second parallel data in accordance with said second routing data.

53. The communications system as recited in claim 52, wherein said sequencer means comprises:

memory means for storing sequencing data; and

counter means, coupled to said memory means, for addressing said buffer means in accordance with said sequencing data.

54. The communications system as recited in claim 53, wherein said control interface means further comprises:

comparator means, coupled to said second bus, for accessing said memory means to provide said sequencing data to said counter means in accordance with said second routing data.

55. The communications system as recited in claim 2, wherein at least one of said plurality of first interfaces and at least one of said plurality of second interfaces comprise:

high level bus extension means, coupled to said first bus means, for providing some of said first parallel data to said first bus means and for receiving said second parallel data from said first bus means.

56. The communications system as recited in claim 55, wherein said high level bus extension means comprises:

comparator means for providing said first parallel data to said first bus means when said first routing data equals a preselected address.

57. The communications system as recited in claim 55, wherein said high level bus extension means comprises:

comparator means for providing enable data when said second routing data equals a preselected address.

58. The communications system as recited in claim 55, wherein said first bus means comprises:

transmit bus means, coupled to said routing means and to said plurality of first interfaces, for providing said first parallel data to said plurality of first interfaces; and

receive bus means, coupled to said routing means and to said plurality of second interfaces, for providing said second parallel data to said plurality of second interfaces.

59. The communications system as recited in claim 55, further comprising:

low level bus extension means, coupled to said high level bus extension means, for providing some of said first parallel data to said high level bus extension means, and for receiving said second parallel data from said high level bus extension means.

60. The communications system as recited in claim 59, wherein said low level bus extension means comprises:

comparator means for providing said first parallel data to said first high level bus extension means when said first routing data equals a preselected address.

61. The communications system as recited in claim 59, wherein said low level bus extension means comprises:

comparator means for providing said first parallel data to said first high level bus extension means when said first routing data equals a preselected address.

62. The communications system as recited in claim 59, wherein said low level bus extension means comprises:

comparator means for providing enable data when said second routing data equals a preselected address.

63. The communications system as recited in claim 3, further comprising:

programming bus means coupled to said control means; and

high level bus extension means, coupled to said first bus means, for providing some of said first parallel data to said first bus means and for receiving said second parallel data from said first bus means.

64. The communications system as recited in claim 63, wherein said high level bus extension means further comprises:

comparator means for providing enable data when data received from said control means via said programming bus means corresponds to a preselected address; and

buffer means, coupled to said programming bus means, for controlling the direction of transmission of data on said programming bus means.

65. The communications system as recited in claim 64, further comprising:

low level bus extension means, coupled to said high level bus extension means, for providing some of said first parallel data to said high level bus extension means, and for receiving said second parallel data from said high level bus extension means.

66. The communications system as recited in claim 65, wherein said low level bus extension means further comprises:

second bus means coupled to said programming bus means;

comparator means for providing enable data when data received from said control means via said programming bus means corresponds to a preselected address; and

buffer means, coupled to said programming bus means, for controlling the direction of transmission of data on said programming bus means.