Automatic bias circuit

• US 4,625,320 A
• Filed: 04/30/1985
• Issued: 11/25/1986
• Est. Priority Date: 04/30/1985
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Butcher, James S.
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US06/728,960
• Time in Patent Office: 574 Days
• Field of Search: 375/76, 375/110, 330/137, 358/171, 307/234, 307/264, 307/359, 328/164
• US Class Current: 375/319
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

An automatic bias control circuit for a data limiter in a synchronous data communications system is disclosed. After word synchronization is achieved, the automatic bias control circuit is enabled and a time relationship between the limited data signal edges and a synchronized local clock signal is detected. The automatically controlled bias level is then modified upward or downward by an additive or subtractive voltage increment for a period of time related to the data bit rate so that the true baseline of the data signal is approximated by the bias level and the detected time relationship is thereby adjusted so that the edges are essentially synchronized with the local clock signal.

Claims

1. An automatic bias control circuit for a synchronous data detector in which the baseline of a data signal input to the automatic bias control circuit is approximated by a bias level, said automatic bias control circuit comprising:

means responsive to the input data signal and said bias level for producing binary data levels, and signals representing data level transition edges;

means for generating local clock signals;

means for detecting a time relationship between said level transition edge representative signals and at least one of said local clock signals; and

means for modifying the bias level in accordance with said detected time relationship thereby causing said data level transition edges to be substantially synchronized with said local clock signals.

2. An automatic bias control circuit in accordance with claim 1 wherein said means for producing binary data levels and signals representing data level transition edges comprises a comparator.

3. An automatic bias control circuit in accordance with claim 2 wherein a capacitor is coupled to said means for modifying the bias level and a noninverting input of said comparator to store a reference bias level for said comparator.

4. An automatic bias control circuit in accordance with claim 1 wherein said means for generating local clock signals further comprises means for synchronizing said local clock signals to the input data.

5. An automatic bias control circuit in accordance with claim 1 wherein said means for generating local clock signals further comprises means for generating at least two clock signals at harmonically related frequencies.

6. An automatic bias control circuit in accordance with claim 1 wherein said means for detecting a time relationship further comprises means for effecting a logical OR function between at least one of said edge representative signals and at least one of said local clock signals.

7. An automatic bias control circuit in accordance with claim 1 further comprising means, coupled to said means for modifying the bias level, for determining whether said bias level should be increased or decreased.

8. An automatic bias control circuit in accordance with claim 1 further comprising:

means for detecting a predetermined binary pattern in the input data;

means for establishing the bias level dependent upon the average magnitude of the data signal during said detection of said predetermined binary pattern; and

means, responsive to said detection of said predetermined binary pattern, to disable said bias level establishing means.

9. A bias contro1 circuit for a data signal limiter of a synchronous data decoder in a radio data communications system in which the baseline wander of the data signal is compensated by a variable bias level, comprising:

means for detecting a predetermined binary pattern in the data signal;

means for establishing a bias level magnitude dependent upon the average magnitude of the data signal;

means for disabling said bias level magnitude establishing means when said predetermined binary pattern is detected;

means responsive to said bias level magnitude for limiting the data signal to produce binary data levels, related to the data signals and to produce signals representing data level transition edges;

means for generating local clock signals synchronized with the data signal no later than the occurrence of said detection of said predetermined binary pattern;

means for detecting a time relationship between said level transition edge representative signals and at least one local clock signal; and

means for modifying said bias level magnitude incrementally in a positive direction each time said time relationship detection indicates a bias level less than the baseline and for modifying said bias level magnitude incrementally in a negative direction each time said time relationship detection indicates a bias level greater than the baseline.

10. A bias control circuit in accordance with claim 9 wherein said means for limiting comprises a comparator in which the data signal is applied to a first input port and the variable bias level is applied to a second input port.

11. A bias control circuit in accordance with claim 10 wherein a capacitor is coupled to said second input port to store said bias level magnitude.

12. A bias control circuit in accordance with claim 9 wherein said means for generating local clock signals further comprises means for generating at least two clock signals at harmonically related frequencies.

13. A bias control circuit in accordance with claim 9 wherein said means for detecting a time relationship further comprises means for effecting a logical OR function between at least one of said edge representative signals and at least one of said local clock signals.

14. A method of biasing a data signal limiter of a synchronous data decoder to compensate baseline wander of the data signal with a bias level, comprising the steps of:

producing binary data levels and signals representing data level transition edges in response to the data signal and said bias level;

generating local clock signals;

detecting a time relationship between said level transition edge representative signals and at least one of said local clock signals; and

modifying the bias level in accordance with said detected time relationship, thereby causing said data level transition edges to be substantially synchronized with said local clock signals.

15. A method in accordance with the method of claim 14 further comprising the steps of:

detecting a predetermined binary pattern in the data signal;

establishing a bias level dependent upon the average magnitude of the data signal; and

ceasing said bias level establishing step when said predetermined binary pattern is detected.

16. A method in accordance with the method of claim 15 further comprising the step of synchronizing said generated local clock signals to the data signal no later than the occurrance of said detection of said predetermined binary pattern.

17. A method in accordance with the method of claim 14 wherein the step of detecting a time relationship further comprises the step of effecting a logical OR function between at least one of said edge representative signals and at least one of said local clock signals.

18. A method in accordance with the method of claim 14 wherein the step of modifying the bias level further comprises the step of incrementally increasing the bias level when said time relationship detection indicates a bias level less than the baseline and incrementally decreasing the bias level when said time relationship detection indicates a bias level greater than the baseline.