Method of making a high voltage DMOS transistor

• US 4,626,293 A
• Filed: 06/27/1984
• Issued: 12/02/1986
• Est. Priority Date: 06/27/1983
• Status: Expired due to Term

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: International Standard Electric Corporation (ITT, Inc.)
• Inventors: Schols, Gustaaf
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/625,723
• Time in Patent Office: 888 Days
• Field of Search: 148/1.5, 148/187, 148/190, 29/576 B, 29/571, 357/23.4, 357/91
• US Class Current: 438/268
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: Y10S 148/082 Ion implantation FETs/COMs

Abstract

A process for manufacturing a high voltage DMOS (Deep Diffusion Metal Oxide Semiconductor) transistor includes a first ion implantation and drive-in step to form a P-well in a N-substrate, and a second such step to form a N+ region in this well and a channel between this region and the substrate and under a polysilicon gate which is covered with a silicon nitride layer during the first step. By the presence of the latter layer pitting of the gate is prevented and no leakage paths are formed between source and drain.

Claims

1. A process for making a semiconductor device comprising the steps of:

providing a substrate of a first conductivity type;

covering said substrate with an oxide layer;

forming a polysilicon gate on said oxide layer;

forming an opening in said oxide layer;

subjecting said substrate to a first predeposition of impurity material of a second conductivity type through said opening;

subjecting said substrate to a first diffusion drive-in operation to form a well of said second conductivity type therein through said opening;

subjecting said substrate to a second predeposition and second diffusion drive-in steps of impurity material to form a region in said well through said opening separated from the boundary of said well by a channel zone, said channel zone being formed under said polysilicon gate;

covering said polysilicon gate by a silicon nitride layer during at least said first drive-in step; and

wherein said region forms the source of said device and said substrate forms the drain of said device.

2. A process in accordance with claim 1 wherein;

said first drive-in step is carried out in a nitrogen atmosphere.

3. A process in accordance with claim 1 wherein said first predeposition step is carried out by ion implantation.

4. A process in accordance with claim 1 wherein:

said first diffusion drive-in is performed at a high temperature of about 1200°

C. for a long duration of about 50 hours.

5. A process in accordance with claim 1 wherein:

said first conductivity type is N type conductivity; and

said second conductivity type is P type conductivity.

6. A process in accordance with claim 4 where said second conductivity type and said impurity material are of P type conductivity.

7. A process for making a semiconductor device comprising the steps of:

providing a substrate of a first conductivity type;

covering said substrate with an oxide layer;

forming a polysilicon gate on said oxide layer;

forming a first and a second opening in said oxide layer;

subjecting said substrate to a first predeposition of impurity material of a second conductivity type through said first opening;

subjecting said substrate to a first diffusion drive-in operation to form a well of said second conductivity type therein through said first opening;

subjecting said substrate to a second predeposition and second diffusion drive-in steps of impurity material through said second opening to form a region separated from the boundary of said well by a channel zone, said channel zone being formed under said polysilicon gate;

covering said polysilicon gate by a silicon nitride layer during at least said first drive-in step; and

wherein said region forms the source of said device and said well forms the drain of said device.