Motion detecting circuit utilizing inter-frame difference signals of successive fields

• US 4,626,891 A
• Filed: 07/23/1984
• Issued: 12/02/1986
• Est. Priority Date: 07/25/1983
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Achiha, Masahiko
• Primary Examiner(s): Shepperd, John W.
• Application Number:
  US06/633,273
• Time in Patent Office: 862 Days
• Field of Search: 358/11, 358/21 R, 358/105
• US Class Current: 348/702
• CPC Class Codes: G06T 7/254 involving subtraction of images
• CPC Class Codes: H04N 19/503 involving temporal prediction adaptive coding with adaptive selection between spatial and temporal predictive coding H04N19/107; adaptive coding with adaptive selection among a plurality of temporal predictive coding modes H04N19/109
• CPC Class Codes: H04N 5/144 Movement detection for video coding H04N19/503; analysis of motion in general G06T7/20

Abstract

A motion detecting circuit suitable for detecting object-movement on an interlaced TV signal includes at least three field memories, subtracters, absolute circuits and an adder circuit. The motion detector evaluates object-movement by accumulating frame difference signals between adjacent fields.

Claims

1. A motion detecting circuit for detecting the motion of an object in an interlaced television signal comprising:

an input terminal to which the interlaced television signal is applied;

a plurality of memories connected in series to said input terminal, the sum of capacities of said plurality of memories corresponding to at least three fields;

a first circuit for calculating at least two inter-frame difference signals of successive fields from said plurality of memories; and

a second circuit for determining the motion of said object by utilizing the output of said first circuit.

2. A motion detecting circuit according to claim 1, wherein said interlaced television signal applied to said input terminal is a monochrome signal or a low frequency signal of a color television signal.

3. A motion detecting circuit according to claim 2, wherein said color television signal is an NTSC color television signal.

4. A motion detecting circuit according to claim 3, wherein said plurality of memories are a first, a second, a third, a fourth, and a fifth memories connected in series in the mentioned order and having 262H, 1H, 262H, 262H, and 1H, said H being a capacity of a scanning line;

wherein said first circuit includes a first subtracter for obtaining the difference between an input signal to said first memory and the output of said third memory, a second subtracter for obtaining the difference between the respective outputs of said first and fourth memories, a third subtracter for obtaining the difference between the respective outputs of said second and fifth memories, and a plurality of absolute value circuits connected to said respective subtracters.

5. A motion detecting circuit according to claim 2, further comprising a band pass filter for extracting a high frequency component of said color television signal including a chrominance subcarrier, a third circuit for receiving the output of said band pass filter and for obtaining one of an inter-field difference signal of high frequency component of said color television signal and an absolute value of said inter-field difference signal, and for obtaining one of an inter-frame difference signal of said inter-field difference signal and an inter-frame difference signal of said absolute value of said inter-field difference signal, and a fourth circuit for producing motion information of the object on the basis of the respective outputs of said second and third circuits.

6. A motion detecting circuit according to claim 5, wherein said third circuit includes a first subtracter for obtaining the difference between the output of said filter and a signal obtained by delaying said output of said filter by one field, and a second subtracter for obtaining the difference between the output of said first subtracter and a signal obtained by delaying said output of said second subtracter by one frame.

7. A motion detecting circuit according to claim 5, wherein said third circuit includes a first subtracter for obtaining the difference between the output of said filter and a signal obtained by delaying said output of said filter by one field, and a first absolute circuit for obtaining an absolute value of the output of said first subtracter, and a second subtracter for obtaining the difference between the output of said first absolute circuit and a signal obtained by delaying said output of said first absolute circuit by one frame.

8. A motion detecting circuit according to claim 5, wherein said third circuit includes a series connection of a first, a second, and a third field memories having delay times of 262H, 263H and 262H, respectively, said series connection having an input connected to the output of said filter, a first subtracter for obtaining the difference between the input and output of said first field memory, a second subtracter for obtaining the difference between the respective outputs of said second field memory and said first subtracter, and an adder for obtaining the sum of the respective outputs of said third field memory and said second subtracter.

9. A motion detecting circuit according to claim 5, wherein said third circuit includes a series connection of a first, a second and a third field memories having delay times of 262H, 263H and 262H, respectively, said series connection having an input connected to the output of said filter, a first subtracter for obtaining the difference between the input and output of said first field memory, a second subtracter for obtaining the difference between the input and output of said third field memory, and a third subtracter for obtaining the different between absolute values of the respective outputs of said first and second subtracters.

10. A motion detecting circuit according to claim 2, wherein said plurality of memories are a first, a second, a third, a fourth, and a fifth memories connected in series in the mentioned order and having 262H, 1H, 262H, 262H, and 1H, said H being a capacity of a scanning line;

wherein said first circuit includes a first subtracter for obtaining the differences between an input signal to said first memory and the output of said third memory, a second subtracter for obtaining the difference between the respective outputs of said first and fourth memories, a third subtractor for obtaining the difference between the respective outputs of said second and fifth memories, and a plurality of absolute value circuits connected to said respective subtracters; and

wherein said second circuit includes an adder for adding outputs of said plurality of absolute value circuits, and a coefficient conversion circuit for converting the output of said adder to a movement coefficient.