Address range determination
First Claim
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1. A circuit for checking to see if a memory address made up of a group of M high order digits plus a group of K low order digits can fall within a range of contiguous memory addresses comprising:
- first means for receiving the low order K-digits of an address at one end of said range of contiguous addresses,second means for receiving c-digits that indicate the number of addresses in said range of contiguous addresses,first logic means responsive both to the K-g high order digits of said K low order digits received in said first means where g is a number of digits less than K digits and equal to or greater than c digits and to the correspondingly ordered K-g high order digits of said lower order digits in the memory address being checked to test for the existence of conditions of the K-g digits which would indicate the memory address can fall within said range and in response to the test provide a first set of signals indicative of the results of the test,second logic means responsive both to said low-order g digits of said K low order digits received in said first means, and to the correspondingly ordered g low order digits of the memory address being checked and also responsive to said c digits received by said second means for testing the occurrence of a particular one of a plurality of further conditions of the g digits which would indicate that the memory address can fall within the range and provide a second set of signals indicative to the results of the testing, andthird logic means responsive to the first and second set of signals from said first and second logic means respectively to determine concurrence of one of the plurality of further conditions with one of the first mentioned conditions and thereby indicate whether said memory address does fall in said range.
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Abstract
An (M plus K)-digit accessed address is checked to see if it may fall within a range of addresses g defined by the address at one end of the range plus a variable range of addresses (g). The checking is done in a single step in a comparison of the K lowest order address digits for both addresses. The K digits of the two addresses are checked against one another in two separate segments, a pointer segment and a range segment. The pointer segments of the two addresses are examined to see if any one of three relationships which would possibly place the accessed address within the range exists. The range segments of the two addresses are examined at the same time for an additional requirement to place the accessed address in the range.
13 Citations
4 Claims
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1. A circuit for checking to see if a memory address made up of a group of M high order digits plus a group of K low order digits can fall within a range of contiguous memory addresses comprising:
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first means for receiving the low order K-digits of an address at one end of said range of contiguous addresses, second means for receiving c-digits that indicate the number of addresses in said range of contiguous addresses, first logic means responsive both to the K-g high order digits of said K low order digits received in said first means where g is a number of digits less than K digits and equal to or greater than c digits and to the correspondingly ordered K-g high order digits of said lower order digits in the memory address being checked to test for the existence of conditions of the K-g digits which would indicate the memory address can fall within said range and in response to the test provide a first set of signals indicative of the results of the test, second logic means responsive both to said low-order g digits of said K low order digits received in said first means, and to the correspondingly ordered g low order digits of the memory address being checked and also responsive to said c digits received by said second means for testing the occurrence of a particular one of a plurality of further conditions of the g digits which would indicate that the memory address can fall within the range and provide a second set of signals indicative to the results of the testing, and third logic means responsive to the first and second set of signals from said first and second logic means respectively to determine concurrence of one of the plurality of further conditions with one of the first mentioned conditions and thereby indicate whether said memory address does fall in said range. - View Dependent Claims (2, 3, 4)
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4. The apparatus of claim 1 wherein,
a first of said first mentioned conditions of said K-g digits is that each of said K-g digits received in said first means is equal to "1" when each of said K-g digits in the memory address is equal to "0", a second of said first mentioned conditions of said K-g digits is that one digit i of the K-g digits of the memory address equals "1" while the corresponding digit i in the K-g digits received in said first means equals "0" while each higher order digit of said K-g digits in said memory address is equal to its corresponding digit of the K-g digits received in said first means and all lower order digits in said K-g digits of the memory address equal "0" and lower order of said K-g digits received in said first means equals "1", a third of said first mentioned conditions of the K-g digits is that each of the digits in the memory address is equal to the corresponding digit in the K-g digits received by said first means, a first of the further conditions equals [(ODR.sub.(M+K-g+1)-(M+K)) minus (ICR.sub.(M+K-g+1)-(M+K) plus RANGE SIZE)< - -2g ]
a second of the further conditions equals [(ICR.sub.(M+K-g+1)-(M+K))≦
(ODR.sub.(M+K-g+1)-(M+K))<
(ICR.sub.(M+K-g+1)-(M+K) plus RANGE SIZE)]said first set of signals are X, Y and Z where X·
Y=the OR of the first and second of the first mentioned conditions and Z·
Y=n the third of the first mentioned conditionswhere said third logic means performs the logical function X·
Y·
A+B·
Y·
Z to determine if the memory address can be within said range.
- -2g ]
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsWeinberger, Arnold, Blount, Frederick T.
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Primary Examiner(s)Chan, Eddie P.
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Application NumberUS06/490,764Time in Patent Office1,310 DaysField of Search364/200 MS File, 364/900 MS File, 365/230US Class Current711/212CPC Class CodesG06F 12/1441 for a rangeG06F 7/026 Magnitude comparison, i.e. ...
