Memory cell power scavenging apparatus and method

• US 4,627,034 A
• Filed: 11/09/1984
• Issued: 12/02/1986
• Est. Priority Date: 11/09/1984
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: Fairchild Camera and Instrument Corporation (ON Semiconductor Corporation)
• Inventors: Herndon, William H.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/669,929
• Time in Patent Office: 753 Days
• Field of Search: 365/226, 365/227, 365/189, 365/230
• US Class Current: 365/226
• CPC Class Codes: G11C 11/414 for memory cells of the bipolar type
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

The present invention utilizes the power available for application to a static RAM cell in a manner which provides efficient use of the power so that greater standby power may be applied to the static RAM to increase the memory speed. The current required to maintain the memory cell in a preset state flows from the U_cc source through a row of parallel memory cells and through a common bias supply and various peripheral circuits, such as decoders. A shunt voltage regulator controls the dependence of the common bias supply voltage on current fluctuations caused by addressing and deaddressing the memory cells. The invention includes an isolation device for isolating a particular row of memory cells when it is addressed without disturbing the bias on other memory cell rows. Similarly, the reference voltages of each of the peripheral circuits can be made independent of the common bias supply voltage and independent of the other peripheral circuits by the use of a local voltage regulator on each peripheral.

Claims

1. A system for efficiently using standby current in a system, comprising:

a single power supply having first and second voltage level outputs;

a memory circuit coupled to one of said voltage level outputs to receive standby power in a deaddressed state;

a common bias supply bus connected to receive standby current from said memory circuit, said common bias supply bus having a voltage level between said first and second voltage level outputs; and

at least one second circuit connected to said common bias supply bus such that at least some of the standby current of said memory circuit may flow through said second circuit to provide a portion of the current required to operate said second circuit.

2. The system of claim 1 further comprising:

means for selectively addressing said memory circuit to read digital data stored therein; and

means for isolating said memory from said common bias supply bus while said memory circuit is addressed.

3. The system of claim 2 wherein said isolating means comprises a resistor connected between said memory circuit and said common bias supply bus.

4. The system of claim 3 further comprising means for biasing said memory circuit to establish a predetermined standby current.

5. The system of claim 4 wherein said biasing means comprises a biasing resistor connected between said memory circuit and said power supply.

6. The system of claim 2 wherein said isolating means comprises a switching device connected between said memory circuit and said common bias supply bus, said switching device being in a conductive state while the standby current flows through said memory circuit, said switching device being in a non-conductive state while said memory cell is addressed to limit the flow of electrical current between the memory circuit and the common bias supply bus.

7. The system of claim 6 wherein said switching device comprises a transistor.

8. The system of claim 6 further comprising a voltage regulator coupled to said common bias supply bus to limit voltage fluctuations thereon as the memory circuit goes between the addressed and deaddressed states.

9. The system of claim 1 wherein the memory circuit comprises an emitter coupled logic circuit.

10. The system of claim 1 further comprising:

a plurality of rows of memory circuits connected to supply standby current from said said common bias supply bus, each said row including a plurality of memory circuits;

means for selectively addressing the rows of memory circuits; and

means for substantially isolating each row of addressed memory circuits from said common bias supply bus such that standby current fluctuations from said rows caused by changes between the addressed and the deaddressed states do not substantially affect the voltage level of said common bias supply bus.

11. The system of claim 10 wherein each of said memory circuits comprises an emitter coupled memory cell.

12. The system of claim 10 wherein each of said memory circuits comprises a diode coupled memory cell.

13. The system of claim 10 further comprising a voltage regulator coupled to said common bias supply bus to limit voltage fluctuations thereon as said rows of memory circuits are addressed and deaddressed.

14. The system of claim 10 wherein said means for isolating comprises a resistor coupled to each said row and selected to have a resistance that is sufficiently high to prevent substantial sinking of current from said common bias supply bus when the row associated with a particular resistor is addressed and a resistance that is sufficiently low so as not to substantially impede the flow of standby current between said row and said common bias supply bus when said row is deaddressed.

15. The system of claim 10 wherein said means for isolating comprises a transistor associated with each row, said transistor having a switching path and switching node for receiving a signal which controls current flow through said switching path, said transistor having its switching path coupled between its associated row and said common bias supply bus and having its switching node coupled to a signal from said means for selectively addressing such that said switching path is conductive when said row is deaddressed and non-conductive when said row is deaddressed.

16. An apparatus for more efficiently utilizing the standby current in a system, comprising:

a single power supply for providing a single voltage level output relative to a reference voltage level;

a first subsystem coupled to draw operating current from said power supply and operating over a first voltage range within the range of voltage between said single voltage level output and said reference voltage level;

a common bias supply bus coupled to said first subsystem to receive said operating current; and

a second subsystem operating over a second voltage range within the range defined by said single voltage level output and said reference voltage level, said second subsystem being coupled to said common bias supply bus to draw operating current therefrom.

17. An apparatus as defined in claim 16 wherein said first and second voltage ranges do not overlap.

18. An apparatus as defined in claim 16, further comprising voltage regulator means coupled to said common bias supply bus to maintain the voltage thereon relatively constant despite fluctuations in the operating current drawn by said first and second subsystems.

22. The method of claim 18 wherein the isolating step comprises the steps of:

connecting a switching device between the memory circuit and the common bias supply bus; and

changing the switching device from a conductive to a non-conductive state as the memory circuit is addressed.

19. A method for supplying standby current from a power source to a static random access memory, comprising the steps of:

passing standby current through a deaddressed memory circuit to a common bias supply bus; and

passing at least part of said standby current from said memory circuit through a circuit coupled to said common bias supply bus.

20. The method of claim 19, further comprising the steps of:

addressing the memory circuit; and

isolating the memory circuit from the common bias supply bus while the memory circuit is addressed.

21. The method of claim 20 wherein the isolating step comprises the step of connecting a resistor between the memory circuit and the common bias supply bus.