Watchdog timer

• US 4,627,060 A
• Filed: 11/29/1984
• Issued: 12/02/1986
• Est. Priority Date: 11/29/1984
• Status: Expired due to Term

• Current Assignee: Baxter Travenol Laboratories Incorporated
• Original Assignee: Baxter Travenol Laboratories Incorporated
• Inventors: Huang, Leon, Selman, John J.
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US06/676,130
• Time in Patent Office: 733 Days
• Field of Search: 371/12, 371/62, 371/14, 371/16, 364/200, 364/900
• US Class Current: 714/36
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day

Abstract

A self-checking timer usable with a host system includes a clock and a plurality of interconnected counters. During a power-up phase the timer generates a system reset signal and counts the counters in a predetermined sequence. A flip-flop is set and reset during the power-up phase and inhibits generation of the system reset signal. During a normal operating phase, the timer generates a test signal that must be responded to by the host system to continuously inhibit generation of the system reset signal.

Claims

1. An apparatus for generating a controlled system reset signal comprising:

first means for sensing an initial application of electrical power and for generating said reset signal;

second means for generating a plurality of clock pulses of a selected frequency;

third means for selectively counting said clock pulses in a selected, predetermined counting sequence; and

fourth means for sensing said predetermined counting sequence including means for setting a selected indicia in response thereto and for inhibiting generation of said reset signal in response thereto.

2. An apparatus as defined in claim 1 further comprising:

fifth means for repetitively generating a test signal when said reset signal is inhibited; and

sixth means for sensing a selected response to said test signal and for blocking generation of the system reset signal provided a selected response to the test signal has been sensed.

3. A timing apparatus for monitoring the start-up and operating functions of a host system comprising:

first means for generating a series of test signals when power is initially supplied to said timing apparatus and for determining if said timing apparatus is functioning properly;

second means for removing a host system reset signal to allow said host system to begin operating after said first means has determined that said timing apparatus is functioning properly;

third means for generating a test signal for transmission to said host system during operation of the host system and to which said host system must properly respond to continue operation of said host system; and

means for generating said system reset signal to halt operation of said host system when said host system does not properly respond to said test signal generated by said third means.

4. An apparatus as recited in claim 3, wherein said third means further comprises:

a valid window generator (24) for continuously generating valid window signals for transmission to said host system and to which said host system must properly respond to continue operation of said host system.

5. An apparatus as recited in claim 4, wherein said first means further comprises:

a first counter (14) for generating uniformly pulsed signals;

a secondary reset counter (28) for receiving and counting said signals from said first ocunter (14) and for generating a signal when said secondary reset counter (28) has counted a preset number of signals from said first counter;

fourth means for transmitting signals from said first counter to said valid window generator (24) to enable said valid window generator (24) in response to said signal from said secondary reset counter (28);

fifth means for transmitting signals from said first counter (14) to said valid window generator (24) after said valid window generator (24) has been enabled to generate said valid window signals;

sixth means for receiving a valid window generator reset signal from said host in response to said valid window signals; and

seventh means for transmitting said valid window generator reset signal to said valid window generator (24) to reset said valid window generator.

6. An apparatus as recited in claim 5 wherein said seventh means further comprises:

eighth means for blocking signals from said first counter (14) to said valid window generator (24) in response to said valid window generator reset signal.

7. An apparatus as recited in claim 3 wherein said third means further comprises:

a first counter (14) for generating uniformly pulsed signals; and

a valid window generator (24) for receiving said signals from said counter (14) and for generating said test signal.