Addressable transducer with improved address signal processing

• US 4,628,315 A
• Filed: 08/16/1983
• Issued: 12/09/1986
• Est. Priority Date: 08/16/1983
• Status: Expired due to Term

• Current Assignee: Sparton Corporation (Elbit Systems Limited)
• Original Assignee: Sparton Corporation (Elbit Systems Limited)
• Inventors: Douglas, Norman F.
• Primary Examiner(s): Ruehl, Charles A.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/523,693
• Time in Patent Office: 1,211 Days
• Field of Search: 340/870.26, 340/825.07, 340/870.02, 340/870.03, 340/825.52, 340/825.6, 340/870.05
• US Class Current: 340/870.26
• CPC Class Codes: H04M 3/28 Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
• CPC Class Codes: H04Q 9/14 Calling by using pulses

Abstract

An addressable transducer is disclosed for use in a monitoring system of the type including a central station and multiple addressable transducers for monitoring physical conditions. The transducer is connected across a single pair of transmission lines having a voltage thereon modulated at controlled intervals to produce successive binary address signals. Each address signal is produced as a level shift, pulsewidth modulation of the line voltage. An address signal processing circuit includes a memory for storing multiple bits of an assigned address signal. A multiplexer coupled with the memory and operated under clock control derived from the transmitted address signal generates a train of pulses representing the stored address signal in bit-by-bit synchronism with the train of pulses of the transmitted address. A match detector pairs the trains of the pulses and a match counter produces a control signal in response to a match of all bits of the addresses. An electronic switch responds to the control signal and energizes a current sink oscillator in the line voltage for producing a modulating current of the transmission line having a frequency corresponding to the measured condition.

Claims

1. An addressable transducer for use in a monitoring system of the type including a central station and multiple addressable transducers for monitoring the values of selected physical conditions at multiple locations with one of said transducers at each of said multiple locations,

said system being characterized by a single pair of transmission lines extending from the central station to all of said multiple locations and having a voltage thereon which is modulated at controlled intervals to produce successive binary address signals each including a train of pulses representing the binary bits of a transmitted address signal for selectively addressing one of the multiple transducers to obtain a data signal therefrom,

said transducer comprising:

a current sink oscillator having a frequency determining circuit for determining the oscillator frequency and being adapted to oscillate in response to application of an operating voltage,

a sensor including a condition responsive impedance element coupled with said frequency determining circuit and adapted to modify said oscillation frequency according to variations in value of said physical condition,

an address signal processing circuit coupled with said pair of lines and including memory means for storing multiple bits of a stored address signal assigned to the transducer, generating means including a clocking means responsive to the pulses of said transmitted address signal for generating a train of pulses representing the binary bits of said stored address signal in bit-by-bit synchronism with the train of pulses of said transmitted address signal, a match detector for comparing said trains of pulses bit-by-bit, and a match counter for producing a control signal in response to a match of all bits of the transmitted address signal with all bits of the stored address signal,

and switching means responsive to said control signal for operatively coupling said oscillator to said pair of lines for deriving an operating voltage therefrom,

whereby said oscillator draws current from said pair of lines, said current having an undulating amplitude at the frequency of the oscillator whereby the frequency of the undulating current in said lines at said central station corresponds to the value of said physical condition.

2. The invention as defined in claim 1 wherein the train of pulses of the transmitted address signal is pulse width modulated,

and said address signal processing circuit includes a one/zero detector coupled with said pair of lines for converting the pulse width modulated address signal to a binary pulse signal representing the transmitted address signal.

3. The invention as defined in claim 2 wherein,

said generating means is a multiplexer including data inputs coupled with said memory means, enabling inputs, and an output coupled with said match detector,

a clock generator for producing a clock pulse corresponding to each pulse of said pulse width modulated binary address signal, and a multiplex counter coupled with said clock generator and having an output coupled with the enabling inputs of said multiplexer, whereby said multiplexer produces said train of pulses representing the binary bits of said assigned address signal in bit-by-bit synchronism with the transmitted address signal.

4. The invention as defined in claim 3 including,

a reset generator including a one shot multivibrator and a logic gate for producing a reset pulse for resetting the match counter and the multiplex counter after receipt of an address signal.