MOS dynamic random access memory
First Claim
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1. A MOS-dynamic random access memory, comprising:
- a semiconductor substrate;
a memory array formed of a plurality of memory cells arranged in a matrix on the substrate, each of said memory cells including a memory capacitor and a switching MOSFET having a gate, a source, a drain, and a channel region doped with impurities of a conductivity type opposite to that of the substrate;
a plurality of word lines formed on the substrate each connected in common with the gates of the switching MOSFETs of a plurality of said memory cells arranged along each corresponding row of said memory array;
a decoder formed on the substrate for selectively driving said plurality of word lines, including an output MOSFET and a flip-flop connected to the source of the output MOSFET, wherein a substrate bias voltage delivered from a back-gate bias circuit is used as a reference potential of said flip-flop;
a clock generator formed on the substrate for controlling the operating timing of the decoder; and
a level shift circuit formed on the substrate connected between an output of said clock generator and the drain of the output MOSFET of said decoder.
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Abstract
In a MOS-dRAM formed by integrating memory cells each formed of an MOS capacitor and an MOSFET, a D-type transistor with a threshold voltage lower than that of MOSFETs of peripheral circuits is used for the MOSFET of each memory cell. Thus, a word line driver without a pull-up circuit can be used, permitting high-speed access of the MOS-dRAM.
19 Citations
1 Claim
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1. A MOS-dynamic random access memory, comprising:
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a semiconductor substrate; a memory array formed of a plurality of memory cells arranged in a matrix on the substrate, each of said memory cells including a memory capacitor and a switching MOSFET having a gate, a source, a drain, and a channel region doped with impurities of a conductivity type opposite to that of the substrate; a plurality of word lines formed on the substrate each connected in common with the gates of the switching MOSFETs of a plurality of said memory cells arranged along each corresponding row of said memory array; a decoder formed on the substrate for selectively driving said plurality of word lines, including an output MOSFET and a flip-flop connected to the source of the output MOSFET, wherein a substrate bias voltage delivered from a back-gate bias circuit is used as a reference potential of said flip-flop; a clock generator formed on the substrate for controlling the operating timing of the decoder; and a level shift circuit formed on the substrate connected between an output of said clock generator and the drain of the output MOSFET of said decoder.
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsSakui, Koji
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Primary Examiner(s)Hecker, Stuart N.
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Assistant Examiner(s)Gossage, Glenn A.
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Application NumberUS06/681,024Time in Patent Office726 DaysField of Search365/149, 365/174, 365/189, 365/178, 357/23.6, 307/449, 307/463US Class Current365/149CPC Class CodesG11C 11/404 with one charge-transfer ga...G11C 11/4076 Timing circuits for regener...G11C 11/4085 Word line control circuits,...
