Dual slope, feedback controlled, EEPROM programming
First Claim
1. A method of programming a floating gate memory cell of the type having a thin-oxide area between a floating gate and another electrode, comprising the steps of:
- applying a voltage to said memory cell to produce an electric field across said thin-oxide area, and increasing said voltage substantially linearly as a function of time at a first rate, abruptly changing the rate of increase of said voltage to a second rate lower than said first rate and then continuing to increase said voltage substantially linearly, then again abruptly ceasing said increase of voltage and thereafter maintaining said voltage constant at a given maximum level for a selected time.
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Accused Products
Abstract
A floating-gate, electrically-erasable, programmable read-only memory cell is programmed or erased by a high voltage across a thin oxide area between the floating gate and the substrate. A tunnelling phenomena is produced by the high voltage. In order to protect the thin oxide from excessive stress, yet minimize programming time, the maximum electric field is controlled by a dual-slope waveform for the programming voltage Vpp. The values of slope and breakpoints for this dual-slope Vpp voltage are selected by a feedback arrangement which is responsive to process variations in threshold voltage, supply voltage, etc.
62 Citations
19 Claims
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1. A method of programming a floating gate memory cell of the type having a thin-oxide area between a floating gate and another electrode, comprising the steps of:
applying a voltage to said memory cell to produce an electric field across said thin-oxide area, and increasing said voltage substantially linearly as a function of time at a first rate, abruptly changing the rate of increase of said voltage to a second rate lower than said first rate and then continuing to increase said voltage substantially linearly, then again abruptly ceasing said increase of voltage and thereafter maintaining said voltage constant at a given maximum level for a selected time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An electrically-erasable, programmable, semiconductor memory cell comprising:
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a control gate, a floating gate and a source-to-drain path at a face of a semiconductor body, write/erase means at said face including an upper electrode integral with said floating gate, and a lower electrode in said face, with a thin oxide area between the upper and lower electrodes, means for applying a programming pulse across said thin-oxide area, said pulse including a first substantially linear ramp period of increasing voltage followed by a second substantially linear ramp period of increasing voltage followed by a period of constant voltage, and abruptly changing from the first to the second at a time related to the electric field across said thin-oxide area. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification