Testing apparatus for redundant memory

• US 4,628,509 A
• Filed: 05/11/1984
• Issued: 12/09/1986
• Est. Priority Date: 05/11/1983
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawaguchi, Ikuo
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/609,445
• Time in Patent Office: 942 Days
• Field of Search: 371/10, 371/21, 371/25, 364/200, 364/900
• US Class Current: 714/711
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

Only that data which relates to detected failures of data stored in a memory under test is stored in a compressed data matrix of a small capacity which is determined by a predetermined number of redundant lines to be selected for remedy of the failures, and the selection of the redundant lines is effected during the execution of a test on the memory. Analysis leading to redundant line selection is effected on the data stored in this compressed matrix.

Claims

1. In an apparatus for testing a redundant memory including means for applying a test pattern to a memory under test which has a matrix of storage cells having X and Y addresses, means for determining failures in the data stored in the storage cells of said memory on the basis of test results obtained by comparing outputs from said memory under test with expected values, and means for remedying said failures along selected redundant lines in the X and/or Y directions of said matrix of storage cells, the improvement comprising:

(a) a compressed data matrix storage device for storing as compressed data only the data relating to failures determined from the test results of said failure determining means;

(b) an address conversion unit which converts the X and Y addresses of said failures detected by said failure determining means into addresses of said compressed data matrix storage device and controls the storing of failure data in said compressed data matrix storage device;

(c) an auxiliary processing unit which judges whether remedy of the failures is possible on the basis of the data of the test results stored in said compressed data matrix storage device and for controlling said remedying means when remedy of the failures is not possible;

(d) means for selecting said redundant lines by analyzing the data in said compressed data matrix storage device and for supplying the identify of said redundant lines to said remedying means; and

(e) means for supplying the data in said compressed data matrix storage device to said remedying means.

2. The apparatus for testing a redundant memory as defined in claim 1 wherein the number x and y of the columns and rows of said compressed data matrix are represented by the following formulas, where N_x and N_y are the numbers of redundant lines on the column and row sides, respectively:

space="preserve" listing-type="equation">x=(N.sub.x ·

N.sub.y)+N.sub.x

space="preserve" listing-type="equation">y=(N.sub.x ·

N.sub.y)+N.sub.y

3. The apparatus for testing a redundant memory as defined in claim 2 wherein said address conversion unit comprises:

(a) a pair of failure line registers which hold the addresses on the column and row sides of the memory under test, respectively;

(b) means including a pair of counters which receive outputs from said pair of failure line registers, respectively, to count the number of new failure addresses generated, to produce an output indicating whether or not the number of addresses of said compressed data matrix is within (x×

y), and to number the failure addresses in accordance with the sequence in which they occurred so that said addresses can be used as addresses of said compressed data matrix;

(e) a pair of address registers which store said addresses obtained from said pair of counters so as to correspond to said failure addresses; and

(f) a decoder which converts one of the address outputs from said pair of address registers as a data input to said compressed data matrix.

4. The apparatus for testing a redundant memory as defined in claim 3 wherein each of said failure line registers comprises a 1-bit wide RAM of a depth equal to the address length of said memory under test.

5. The apparatus for testing a redundant memory as defined in claim 3 wherein each of said auxiliary processing unit includes at least:

(a) a pair of comparators which detect whether a new failure address obtained from said pair of counters is outside the dimensions (x×

y) of said compressed data matrix;

(b) a pair of line failure counters which select a redundant line of said memory under test when it is detected that at least (N_x +1) or N_y +1) failures are aligned on the same line of said memory under test;

(c) means including a group of gates which receive outputs from said pair of line failure counters and outputs from said pair of comparators for determining that said memory under test is not acceptable when there is a failure outside the dimensions of said compressed data matrix and a selection of a redundant line has not been made; and

(d) gates provided in a stage before said line failure counters, which prevent double-counting when failures are detected at the same address.

6. The apparatus for testing a redundant memory as defined in claim 5 wherein said pair of line failure counters comprise N_x (or N_y) RAMs that constitute said failure line registers.

7. The apparatus for testing a redundant memory as defined in claim 5, further including redundant line counters for counting the number of selected redundant lines provided in an output stage of said line failure counters.

8. The apparatus for testing a redundant memory as defined in claim 5 which further includes remedy-decision line memories which store subsequent failure dots on the same line after said line failure counters have selected a redundant line.

9. The apparatus for testing a redundant memory as defined in claim 8 wherein each of said remedy-decision line memories comprises N_x line memories of the actual address length of the memory under test and N_y line memories of the actual address length of said memory under test.

10. The apparatus for testing a redundant memory as defined in claim 8 wherein one of said remedy-decision line memories is a memory consisting of N_x line memories on the column side, is formed by extending said compressed data matrix on the row side, and which is of the actual address length of said memory under test.

11. The apparatus for testing a redundant memory as defined in claim 8 wherein one of said remedy-decision line memories is a memory formed by extending said compressed data matrix on the column side, consists of N_y line memories on the row side, and which is of the actual address length of said memory being tested.

12. The apparatus for testing a redundant memory as defined in claim 8 wherein said remedy-decision line memory is a single memory formed by extending the widths on both column and row sides of said compressed data matrix to the actual address length of said memory being tested.