MOS dynamic ram

• US 4,630,088 A
• Filed: 04/03/1985
• Issued: 12/16/1986
• Est. Priority Date: 09/11/1984
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Momodomi, Masaki, Ogura, Mitsugi
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US06/719,450
• Time in Patent Office: 622 Days
• Field of Search: 357/23.4, 357/23.6, 357/41, 357/55, 357/56, 365/149
• US Class Current: 257/302
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: Y10S 257/911 Light sensitive array adapted to be scanned by electron beam, e.g. vidicon device
• CPC Class Codes: Y10S 257/92 Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

A MOS dynamic RAM consists of integrated memory cells each having a MOSFET and a MOS capacitor. The MOS dynamic RAM comprises a semiconductor substrate of a first conductivity type on which periodic projections and recesses are formed, a source region of a second conductivity type formed in the upper surface of each projection, a drain region of the second conductivity type formed in a bottom portion of each projection, a channel region of the first conductivity type sandwiched between the source and drain regions, a gate insulating film formed on a side wall of each projection between the source and drain regions, a gate electrode formed on the gate insulating film, a first insulating film formed on the source region, and a first electrode of the MOS capacitor formed on the first insulating film. The MOSFET is constituted by the source, drain and channel regions, the gate insulating film and the gate electrode. The MOS capacitor is constituted by the source region, the first insulating film and the first electrode, and the source region serves as the second electrode thereof. The gate electrodes serve as word lines, and the first electrodes of MOS capacitor serve as bit lines.

Claims

1. A MOS dynamic RAM constructed by integrated memory cells each having a MOSFET and a MOS capacitor comprising:

a semiconductor substrate of a first conductivity type in which recesses and projections are periodically formed;

a source region of a second conductivity type formed in an upper surface of each of said projections;

a drain region of the second conductivity type formed in a bottom portion of each of said projections;

a channel region of the first conductivity type sandwiched between said source and drain regions;

a gate insulating film formed on a side wall of each of said projections between said source and drain region;

a gate electrode formed on said gate insulating film, said MOSFET being constituted by said source, drain, and channel regions, said gate insulating film and said gate electrode;

a first insulating film formed on said source region;

a first electrode of said MOS capacitor formed on said first insulating film, said MOS capacitor being constituted by said source region, said first insulating film and said first electrode, said source region serving as a second electrode of said MOS capacitor, said gate electrode serving as a word line, and said first electrode of said MOS capacitor serving as a bit line.

2. A MOS dynamic RAM according to claim 1, wherein said channel region is separated from said semiconductor substrate by said drain region.

3. A MOS dynamic RAM according to claim 2, wherein said drain region is formed by a high impurity concentration layer which is common to all memory cells.

4. A MOS dynamic RAM according to claim 2, wherein a plurality of source regions of the second conductivity type are formed in the upper surface of each of said projections to be spaced apart from each other and to extend along the side walls of each of said projections;

and

said MOS dynamic RAM further comprises a high impurity concentration layer of the first conductivity type formed in the upper surface of each of said projections and between said source regions, said high impurity concentration layer being connected to said channel region and a fixed potential being applied thereto so as to prevent floating of said channel region.

5. A MOS dynamic RAM according to claim 1, wherein said drain region of the MOSFET is formed by a high impurity concentration layer which is common to all memory cells;

said gate electrodes are formed by first polycrystalline silicon films and aligned along a column direction so as to constitute said word line;

said source regions which serve as said second electrodes of the MOS capacitors are independently formed for the corresponding memory cells; and

said first electrodes of the MOS capacitor are formed by second polycrystalline silicon films and aligned along a row direction so as to constitute said bit line.

6. A MOS dynamic RAM according to claim 1, wherein said drain region of the MOSFET is formed by a high impurity concentration layer which is common to all memory cells;

said gate electrodes are formed by first polycrystalline silicon films and aligned along a column direction so as to constitute said word line;

said source regions which serve as said second electrodes of the MOS capacitors are independently formed for the corresponding memory cells; and

said first electrodes of the MOS capacitors are independently formed for the corresponding memory cells, and said first electrodes are commonly connected to a metal wiring layer along a row direction so as to constitute said bit line.

7. A MOS dynamic RAM according to claim 1, wherein

said source region is formed to cover the overall surface of each of said projections;

said drain region is formed to cover the overall bottom portion of each of said projections; and

said channel region is sandwiched by said source and drain regions and is separated from said semiconductor substrate through said drain region.

8. A MOS dynamic RAM according to claim 7, wherein said gate electrode includes

a first gate electrode member formed on a first side wall of each of said projections through said gate insulating film;

and

a second gate electrode member formed on a second side wall of each of said projections through said gate insulating film;

the same potential being supplied to said first and second gate electrode members.

9. A MOS dynamic RAM according to claim 7, wherein said first electrode of the MOS capacitor is provided on the upper and side surfaces of said source region through said first insulating film.

10. A MOS dynamic RAM according to claim 1, wherein

a plurality of source regions of the second conductivity type are respectively formed in the upper surface of each of said projections so as to be spaced apart from each other and to extend along the side walls of each of said projections;

said drain region of the MOSFET is formed by a layer common to all the memory cells;

said gate electrode is formed along opposing side walls of two adjacent projections through said gate insulating film; and

each MOSFET is constituted by a pair of source regions formed along opposing side walls of the two adjacent projections, said gate electrode and said drain region.

11. A MOS dynamic RAM according to claim 10, further comprising

a high impurity concentration layer of the first conductivity type provided between said pair of source regions formed in the upper surface of each of said projections, said high impurity concentration layer being connected to said channel region and a fixed potential being applied thereto so as to prevent floating of said channel region.

12. A MOS dynamic RAM according to claim 10, further comprising

electrode means, which overlaps through a second insulating film said gate electrode corresponding to said pair of source regions formed along the opposing side walls of the two adjacent projections, for connecting said pair of source regions, said electrode means serving as a second electrode of the MOS capacitor.

13. A MOS dynamic RAM according to claim 12, further comprising

a high impurity concentration layer of the first conductivity type formed between said pair of source regions provided in the upper surface of each of said projections, said high impurity concentration layer being connected to said channel region and a fixed potential being applied thereto so as to prevent floating of said channel region.

14. A MOS dynamic RAM according to claim 1, wherein said recesses and said projections are periodically formed into stripe forms.

15. A MOS dynamic RAM according to claim 14, wherein

a plurality of source regions of the second conductivity type are formed in the upper surface of each of said projections so as to be spaced apart from each other and to extend along the side walls of each of said projections;

said drain region of the MOSFET is formed by a layer which is common to all the memory cells;

said gate electrode is provided along the opposing side walls of the two adjacent projections in a stripe form through said gate insulating film, said gate electrode being common to the MOSFETs formed along the side walls of each of the recesses; and

each MOSFET is constituted by a pair of source regions which are provided along the opposing side walls of the two adjacent projections, said gate electrode of the stripe form and said drain region.

16. A MOS dynamic RAM according to claim 15, further comprising

a high impurity concentration layer of the first conductivity type formed between said pair of source regions formed in the upper surface of each of said projections, said high impurity concentration layer being connected to said channel region and a fixed potential being applied thereto so as to prevent floating of said channel region.

17. A MOS dynamic RAM according to claim 15, further comprising

electrode means, which overlaps through a second insulating film said gate electrode corresponding to said pair of source regions formed along the opposing side walls of the two adjacent projections, for connecting said pair of source regions, said electrode means serving as a second electrode of the MOS capacitor.

18. A MOS dynamic RAM according to claim 17, further comprising

a high impurity concentration layer of the first conductivity type formed between said pair of source regions formed in the upper surface of each of said projections, said high impurity concentration layer being connected to said channel region and a fixed potential being applied thereto so as to prevent floating of said channel region.

19. A MOS dynamic RAM according to claim 17, wherein said recesses in the stripe forms are V-shaped grooves;

said gate electrodes of the MOSFETs formed in said V-shaped grooves are continuously arranged therein so as to form said word lines; and

said first electrodes of the MOS capacitors are continuously arranged along a direction perpendicular to said V-shaped grooves so as to form said bit lines.

20. A MOS dynamic RAM according to claim 14, wherein a plurality of source regions of the second conductivity type are formed in the upper surface of each of said projections so as to be spaced apart from each other and to extend along the side walls of each of said projections;

said drain region of the MOSFET is formed by a layer which is common to all the memory cells;

said gate electrodes of the MOSFETs are formed in a stripe form along both walls of each of said projections through said gate insulating film, each of said gate electrodes being common to the MOSFETs formed along one side wall of each of said projections; and

each MOSFET is constituted by said source region, said gate electrode which is formed on one side wall of the projection in which said source region is provided, and said drain region.

21. A MOS dynamic RAM according to claim 20, further comprising

a high impurity concentration layer of the first conductivity type formed between said pair of source regions formed in the upper surface of each of said projections, said high impurity concentration layer being connected to said channel region and a fixed potential being applied thereto so as to prevent floating of said channel region.

22. A MOS dynamic RAM according to claim 21, wherein

said gate electrode are continuously aligned along two side walls of said projections so as to constitute different word lines;

and

said first electrodes of the MOS capacitors are continuously aligned along a direction perpendicular to said gate electrodes so as to constitute bit lines.

23. A MOS dynamic RAM according to claim 20, wherein a groove is formed between said source regions formed in the upper surface of each of said projections, said first electrode is formed on an inner surface of said groove through said first insulating film, so that side surfaces of said source regions serve as second electrodes of the MOS capacitors.

24. A MOS dynamic RAM according to claim 23, further comprising

a high impurity concentration layer formed in a bottom surface of said groove, said high impurity concentration layer being connected to said channel region and a fixed potential being applied thereto so as to prevent floating of said channel region.

25. A MOS dynamic RAM according to claim 1, wherein said recesses are V-shaped grooves.

26. A MOS dynamic RAM according to claim 25, wherein said drain region is formed in a bottom surface of each of said V-shaped grooves.

27. A MOS dynamic RAM according to claim 1, wherein said semiconductor substrate comprises a three-layered structure having

a starting substrate of the first conductivity type,

a second conductivity type layer having a high impurity concentration formed on said starting substrate, and

a first conductivity type layer having a low impurity concentration formed on said second conductivity type layer;

said recesses are grooves having a depth from a surface of said first conductivity type layer to said second conductivity type layer;

said second conductivity type layer commonly serves as said drain region of each MOSFET for each memory cell;

said first conductivity type layer serves as said channel region of each MOSFET; and

said source region is formed in a surface of said first conductivity type layer on an upper portion of each of said projections.