Time multiplexed processor bus
First Claim
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1. A synchronous data processing system comprising:
- N processor modules, each processor module including a processor and interface circuitry connected with the processor;
at least one resource module available for access by the processor modules;
a signal global microprocessor bus system commonly shared by the resource module and each of the processor modules, the resource module and the interface circuitry of each of the processor modules being connected in parallel to the bus system to enable communication among the processor modules and between the processor modules and the resource module; and
system timing means connected with the bus system for dividing a predetermined bus cycle time period into N equal time slices, each processor module being granted access to the global bus for a single time slice during each bus cycle time period;
the interface circuitry of each processor module being configured to permit each processor to execute data received from a resource module directly as an instruction and being configured to enable each processor module to communicate information in signle word messages during the processor module'"'"'s respective time slice so that the length of communication among any two of the processor modules and between any processor module and the resource module does not inhibit access by any other processor module to the resource module and to either of said two processor modules.
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Abstract
A multi-master processor bus and a method of processing data which permits multiple microprocessors to communicate freely and inexpensively among themselves and various system resources. The bus uses a multiphase clock and latches to provide time slice signals to sequentially activate each processor, one at a time in a repetitive sequence. The bus includes cables and terminals for each of the cables with means for interconnecting each of the modules in series daisy chain fashion to selected cables.
120 Citations
8 Claims
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1. A synchronous data processing system comprising:
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N processor modules, each processor module including a processor and interface circuitry connected with the processor; at least one resource module available for access by the processor modules; a signal global microprocessor bus system commonly shared by the resource module and each of the processor modules, the resource module and the interface circuitry of each of the processor modules being connected in parallel to the bus system to enable communication among the processor modules and between the processor modules and the resource module; and system timing means connected with the bus system for dividing a predetermined bus cycle time period into N equal time slices, each processor module being granted access to the global bus for a single time slice during each bus cycle time period; the interface circuitry of each processor module being configured to permit each processor to execute data received from a resource module directly as an instruction and being configured to enable each processor module to communicate information in signle word messages during the processor module'"'"'s respective time slice so that the length of communication among any two of the processor modules and between any processor module and the resource module does not inhibit access by any other processor module to the resource module and to either of said two processor modules. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A synchronous data processing system comprising:
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N processor modules, each processor module including a processor and interface circuitry connected with the processor; a single global microprocessor bus system commonly shared by each of the processor modules, the interface circuitry of each of the processor modules being connected in parallel to the bus system to enable communication among the processor modules; system timing means connected with the bus system for dividing a predetermined bus cycle time period into N equal time slices, each processor module being granted to access to the global bus for a single time slice during each bus cycle time period; the interface circuitry of each processor module being configured to enable each processor module to communicate information in single word messages during the processor module'"'"'s respective time slice so that the length of communication between any two processor modules does not inhibit access by any other processor module to either of said two processor modules.
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Specification