Circuit for the fast calculation of the discrete Fourier transform of a signal

• US 4,630,229 A
• Filed: 02/18/1983
• Issued: 12/16/1986
• Est. Priority Date: 02/23/1982
• Status: Expired due to Fees

• Current Assignee: Intercontrole Societe Anonyme
• Original Assignee: Intercontrole Societe Anonyme
• Inventors: D'Hondt, Jean-Pierre
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Shaw, Dale M.
• Application Number:
  US06/467,761
• Time in Patent Office: 1,397 Days
• Field of Search: 364/576, 364/725, 364/726, 364/827
• US Class Current: 708/405
• CPC Class Codes: G01N 27/9046 by analysing electrical signals
• CPC Class Codes: G06F 17/141 Discrete Fourier transforms

Abstract

A circuit for the rapid calculation of the real and imaginary parts of the h first harmonics of a signal supplied by a measuring device and particularly for the analysis of the voltage supplied by a non-destructive eddy current testing probe. The circuit comprises an analog-digital converter, a random access memory, and calculating means comprising a PROM, a counter, a multiplier, an accumulator and a sequencer.

Claims

1. A circuit for the rapid calculation of the real and imaginary parts of the h first harmonics, h being 3 at most, of a signal supplied by a measuring device, particularly a non-destructive eddy-current testing device, said circuit comprising:

an analog-digital converter having an input receiving the signal to be processed and an output supplying digital samples,

a random access, acquisition memory having a data input connected to the output of the converter, an addressing input and a data output,

means for calculating the discrete Fourier transform having an input connected to the output of the acquisition memory and an output supplying the real part and the imaginary part of the harmonics of the signal, said means for calculating the discrete Fourier transform comprising;

a programmable read-only, coefficient memory having an addressing input and a data input, said coefficient memory being subdivided into h blocks, the kth block, with k integer between l and h, containing the coefficients sin 2π

nk/N and cos 2π

nk/N, in which N is the number of samples contained in the acquisition memory and in which n assumes all the values ranging from 0 to N-1,

a counter having two outputs carrying two sets of addresses, the first output being connected to the addressing input of the acquisition memory and the second to the addressing input of the coefficient memory, said addresses respectively corresponding to the samples of the acquisition memory and to the coefficients of a coefficient memory block,

a multiplier circuit having two inputs, one connected to the output of the acquisition memory, the other connected to the output of the coefficient memory, and an output,

an accumulator circuit having an input connected to the output of the multiplier circuit and an output carrying the sought real and imaginary parts,

a sequencer circuit able to transmit pulses to the counter, to control the reading of the samples in the acquisition memory and, simultaneously, the reading in the first block of the coefficient memory of the coefficients cos 2π

n/N, and then to against control the reading of the samples in the acquisition memory and simultaneously the reading in the first block of the coefficient memory of coefficients sin 2π

n/N and, for each reading of the sample and a coefficient, to control the multiplier and then the accumulator and then reiterate the controlling and reading with the second block of the coefficient memory and so on up to the last block.

2. A circuit according to claim 1, comprising, connected to the accumulator output, a mathematical calculation microprocessor able to perform the following operations:

raising to the square of the real and imaginary parts received from the accumulator,

addition of the squares obtained,

extraction of the square root from the sum obtained,

calculation of the quotient of the imaginary part by the real part, and

calculation of the arc tangent of the quotient obtained.

3. A circuit according to claim 1, comprising a microprocessor having accesses to the memories, to the counter, to the multiplier, to the accumulator and to the sequencer.

4. A circuit according to claim 1, wherein the multiplier and accumulator are constituted by the same integrated circuit.