MISFET with input amplifier

• US 4,631,565 A
• Filed: 12/02/1983
• Issued: 12/23/1986
• Est. Priority Date: 01/19/1983
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Tihanyi, Jeno
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/557,712
• Time in Patent Office: 1,117 Days
• Field of Search: 357/23.4, 357/42, 357/46, 357/43, 357/23.14
• US Class Current: 257/338
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A power FET is preceded by an input amplifier consisting of a second FET of the same channel type and a third FET of an opposite channel type. The FETs of the pre-amplifier can be integrated into the chip of the power FET without additional production steps if the power FET and the second FET are designed as vertical FETs and the third FET as a lateral FET. Through this semiconductor device, the relatively high input capacitance of power MISFETs, which results in slow switching speeds when driven by standard ICs, is overcome.

Claims

1. A semiconductor device having a substrate, the substrate containing a first vertical MISFET of a first channel type including a first source zone and a gate zone controlled by a gate electrode, the drain zone of the first vertical MISFET is formed by the substrate, the first source zone and the gate zone extending from a first surface of said substrate into said substrate, an improvement comprising:

(a) a second vertical MISFET of said first channel type including a second source zone and a gate zone controlled by a gate electrode, the drain zone of the second vertical MISFET is formed by said substrate said second source zone and the gate zone of said second MISFET extending from said first surface into said substrate;

(b) a lateral MISFET of a second channel type with a source zone located on the first surface of said substrate and a drain zone located on the first surface, said source zones of said second vertical MISFET and of said lateral MISFET being electrically connected to each other and to the gate electrode of said first vertical MISFET, the gate electrodes of said lateral MISFET and of said second vertical MISFET being electrically connected to each other, and the drain zone of said lateral MISFET being electrically connected to the source zone of said first vertical MISFET;

(c) said gate zone of said first vertical MISFET and said drain zone of said lateral MISFET being a single zone and said source zone of said lateral MISFET and said gate zone of said second vertical MISFET being a single zone;

(d) the first source zone embedded in said drain zone of said lateral MISFET and bounded by the first surface and the second source zone embedded in said source zone of said lateral MISFET and being of an opposite conductivity type thereto; and

(e) a first contact electrically connected to the first source zone of said first vertical MISFET and being electrically connected to said drain zone of said lateral MISFET, and a second contact electrically connected to the second source zone of said second vertical MISFET and being electrically connected to the source zone of said lateral MISFET.

2. A semiconductor device according to claim 1, wherein said substrate comprises a plurality of parallel-connected first vertical MISFETs and wherein said second vertical MISFET and said lateral MISFET are formed in a ring shape and are arranged between the edge of said substrate and said first vertical MISFET adjacent to said edge.

3. The semiconductor device of claim 2, wherein the first vertical MISFET is a power device and the second vertical MISFET and the lateral MISFET serve as an input amplifier to the first vertical MISFET.

4. A semiconductor device according to claim 1, wherein said substrate comprises a plurality of parallel-connected first vertical MISFETs and wherein said second vertical MISFET and said lateral MISFET occupy a substrate area left free by first vertical MISFETs.

5. The semiconductor device of claim 4, wherein the first vertical MISFET is a power device and the second vertical MISFET and the lateral MISFET serve as an input amplifier to the first vertical MISFET.

6. The semiconductor device of claim 1, wherein the first vertical MISFET is a power device and the second vertical MISFET and the lateral MISFET serve as an input amplifier to the first vertical MISFET.