Digital raster timing encoder/decoder
First Claim
1. A digital raster timing encoder/decoder system, for generating horizontal and vertical control synchronization signals for a video raster scan and other preselected timing and digital data signals for said video scan, comprising:
- a clock source;
an encoding means connected to receive a clock signal from the clock source, said encoding means being preprogrammed to encode preselected digital signals to be output by said encoding means; and
a decoding means disposed to receive the encoded digital signals which are output by said encoding means, said decoding means programmed to decode the digital signals;
whereinthe encoding means further comprises;
first means for counting connected to receive the clock source signal, said counting means disposed to accumulate count related to the time progression for horizontal video scan segments;
second means for counting connected to the output of the first counting means, said second counting means disposed to accumulate count in reference to the vertical control synchronization signals of the video raster scan;
first memory means connected to receive digital count signals from the first and second counting means;
second memory means connected to receive said digital count signals from the first and second counting means;
first means for registering, connected to receive said digital count signal from the second means for counting, a first digital timing signal from the first memory means, and also connected to receive the clock source signal, said first registering means storing said digital count signal for output; and
second means for registering connected to receive the stored digital count signal output from the first registering means, a second digital timing signal from the first memory means, said signal from the clock source, and a digital code signal from the second memory means, said second registering means encoding said code signal ahead of the digital count signal output from the first registering means, said second registering means outputting said encoded digital signals to said decoding means.
1 Assignment
0 Petitions
Accused Products
Abstract
The invention presents a digital raster timing encoder/decoder system when television raster synchronization pulses and other timing pulses and information data are generated. The invention comprises a digital clock source having coding circuitry which, combined with the clock source, encodes preselected digital signals containing information on raster synchronization control and timing, and also any other information data that is desired. The encoded signal output is transmitted either directly or via some special transmission link, for example by use of a Manchester Decoder clock multiplier (MDCM) system, to a receiving and decoding circuit. The received signal is decoded to create timing signals for operation control of the video television scanning system, and to read out other desired digital data that has been also transmitted within the signal. The system takes advantage of the fact that control signals of conventional synchronization pulses contain large deadband areas within which additional data information may be placed. Such additional digital information may be used to add other control pulse capability, or to add information transmission capability. A principal feature of the system is that only a single channel is needed to transmit synchronization pulses and any additional timing pulses or information of interest.
19 Citations
16 Claims
-
1. A digital raster timing encoder/decoder system, for generating horizontal and vertical control synchronization signals for a video raster scan and other preselected timing and digital data signals for said video scan, comprising:
-
a clock source; an encoding means connected to receive a clock signal from the clock source, said encoding means being preprogrammed to encode preselected digital signals to be output by said encoding means; and a decoding means disposed to receive the encoded digital signals which are output by said encoding means, said decoding means programmed to decode the digital signals;
whereinthe encoding means further comprises; first means for counting connected to receive the clock source signal, said counting means disposed to accumulate count related to the time progression for horizontal video scan segments; second means for counting connected to the output of the first counting means, said second counting means disposed to accumulate count in reference to the vertical control synchronization signals of the video raster scan; first memory means connected to receive digital count signals from the first and second counting means; second memory means connected to receive said digital count signals from the first and second counting means; first means for registering, connected to receive said digital count signal from the second means for counting, a first digital timing signal from the first memory means, and also connected to receive the clock source signal, said first registering means storing said digital count signal for output; and second means for registering connected to receive the stored digital count signal output from the first registering means, a second digital timing signal from the first memory means, said signal from the clock source, and a digital code signal from the second memory means, said second registering means encoding said code signal ahead of the digital count signal output from the first registering means, said second registering means outputting said encoded digital signals to said decoding means. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A digital raster timing encoder/decoder system for generating horizontal and vertical control synchronization signals for a video raster scan system, and other preselected timing and digital data signals for said video scan, comprising:
-
a clock source; an encoding means connected to receive a clock signal from the clock source, said encoding means being preprogrammed to encode preselected digital signals to be output by said encoding means; and a decoding means disposed to receive the encoded digital signals which are output by said encoding means, said decoding means programmed to decode with digital signals;
whereinthe encoding means further comprises; first means for counting, connected to receive the clock source signal, said counting means predisposed to accumulate count related to the time progression for horizontal video scan segments; second means for counting, connected to the output of the first counting means, said second counting means disposed to accumulate count in reference to the vertical control synchronization signals of the video raster scan; first memory means connected to receive digital count signals from the first and second counting means; second memory means connected to receive said digital count signals from the first and second counting means; means for generating a digital data signal; first means for registering connected to receive said digital data signal from the generating means, a first coded digital timing signal from the first memory means, and also connected to receive the clock source signal, said first registering means storing said digital data signal, from the means for generating, for output; second means for registering, connected to receive the stored signal output from the first registering means, said first digital timing signal from the first memory means, and also the signal from said clock source, said second registering means encoding a first digital signal comprising a logic 1 ahead of the stored signal output from the first registering means, said second registering means connected to output a first composite digital signal; third means for registering, connected to receive and store for output the first composite digital signal output from the second registering means, a coded digital count signal from the second memory means, a second digital timing signal from the first memory means, and also connected to receive the clock source signal; and fourth means for registering, connected to receive the stored signal output from the third registering means, said second digital timing signal from the first memory means, and also the clock source signal, said fourth registering means encoding a second digital signal, comprising a logic 1, ahead of the signal output from the third registering means, said fourth registering means outputting a second composite digital signal to said decoding means. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
-
Specification