Memory interface with automatic delay state
First Claim
1. In a digital processing system including a processor with an internal clock and an external memory, a memory interface connected between the processor and external memory, the memory interface comprising:
- an information transfer bus operably connected between the processor and the external memory for transferring of information between the processor and the external memory;
control means connected to the information transfer bus and the processor for generating at least one control signal for synchronously controlling the transfer of information on the information bus by controlling the time at which the processor reads information from the external memory;
flip-flop means having a first logic state and a second logic state for selecting whether to time delay the control signal; and
wait circuit connected to said control means and said flip flop means for delaying the control signal by a first time delay when the flip flop means is at the first logic state.
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Abstract
A digital processor system that includes a processor interface to an external memory. The interface to the external memory includes an information transfer bus to transfer information between the processor and the external memory and control circuitry to regulate the information on the information bus. This control circuitry includes the capability to delay the reading of information on the memory in order to allow for memory accesses to a slow memory. This delay capability is a selectable feature that is selected upon initialization of the processor.
69 Citations
5 Claims
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1. In a digital processing system including a processor with an internal clock and an external memory, a memory interface connected between the processor and external memory, the memory interface comprising:
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an information transfer bus operably connected between the processor and the external memory for transferring of information between the processor and the external memory; control means connected to the information transfer bus and the processor for generating at least one control signal for synchronously controlling the transfer of information on the information bus by controlling the time at which the processor reads information from the external memory; flip-flop means having a first logic state and a second logic state for selecting whether to time delay the control signal; and wait circuit connected to said control means and said flip flop means for delaying the control signal by a first time delay when the flip flop means is at the first logic state. - View Dependent Claims (2, 3, 4, 5)
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Specification