Data transfer network for variable protocol management

• US 4,631,666 A
• Filed: 10/25/1982
• Issued: 12/23/1986
• Est. Priority Date: 10/25/1982
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Jevons, Lyle O. Jr., Loskorn, Richard A., Harris, Craig W.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Salotto, John J.
• Application Number:
  US06/436,710
• Time in Patent Office: 1,520 Days
• Field of Search: 364/200 MS File, 364/200, 364/900
• US Class Current: 709/217
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A data transfer network uses an I/O subsystem to support a main host computer in managing data transfers to and from remote data terminals. The I/O subsystem may constitute one or more units called a Line Support Processor. The Line Support Processor uses internal processor means to control a plurality of line adapters each of which has a data-comm line to a data set or data terminal. Control operations by said internal processor permit selected line adapters to operate selected types of protocols using synchronous or asynchronous transmission. Data communication information and commands in high level language data are loaded into auxiliary memories in the internal processor means and into each line adapter where the internal processor means acts to convert this language data into usable protocols.

Claims

1. A data transfer network for data transfers between a main host computer and a plurality of remote data sets operating under different protocol and timing disciplines wherein said main host computer initiates I/O data transfer commands to a line support processor means having a plurality of line support processors, each one of which manages data transfers between one of said remote data sets and said main host computer, said data transfer network comprising:

(a) said main host computer connected to each one of said line support processors and including;

(a1) main memory means for storing data to be transmitted to/received from said remote data sets and including;

(a1a) a first dedicated memory area for storing a I/O data transfer commands for transmittal to said line support processors;

(a1b) a second dedicated memory area for storing operational codes for transmittal to said line support processors wherein said operational codes contain information translatable, by said line support processor, into control data for selecting timing and protocol discipline for a selected line adapter;

(a2) a main processor for selecting said I/O data transfer commands and said operational codes for communication and control of said line support processor, said processor including;

(a2a) connection means to a distribution control circuit;

(b) a base module providing backplane connection means for slide-in circuitry cards, said base module including;

(b1) said distribution control circuit functioning to connect and/or disconnect said host computer to/from a selected line support processor in line support processor means;

(b2) said line support processor means functioning to execute said I/O data transfer commands by controlling a selected line adapter to a remote data set, said line support processor means including;

(b2a) a plurality of line support processors connected to said distribution control circuit wherein each said line support processor includes;

(B2a1) interface circuit means connecting said main host computer, via said distribution control circuit, to a plurality of line adapter means and to a state machine processor means;

(b2a2) said state machine processor means including a state machine processor operating to translate said operational codes into control data for operating a selected line adapter in a desired timing and protocol discipline for managing data transfers between said selected line adapter and an associated said data set, said state machine processor means including;

(i) a first auxiliary memory storage area for receiving said operational codes from said host computer;

(ii) program memory means for enabling said state machine processor to translate said operation codes into control data for operating a selected line adapter;

(iii) said state machine processor operating to transmit said control data to said selected line adapter for selecting and managing the timing and protocol discipline for data transfers, and including;

(ie) means for selecting a particular line adapter in said plurality of line adapter means;

(iie) means for identifying the required timing and protocol discipline for said particular line adapter;

(iiie) means for generating address signals for selecting a desired control register in said particular line adapter and placing said control data therein;

(ive) means for transferring data to/from said particular line adapter;

(ve) means for selecting a group of multiplexors associated with said selected particular line adapter;

(c) said plurality of line adapter means connected to said state machine processor means and including a plurality of line adapters, wherein each line adapter includes;

(c1) a data communication line to an associated said remote data set;

(c2) a plurality of control registers holding said control data for managing data transfers according to a desired timing and protocol discipline, said control data being derived from said state machine processor means;

(d) transceiver-controller means, operating under control of said state machine processor means, for switching a data bus to connect said state machine processor to a selected line adapter or to connect said selected line adapter to a multiplexor means;

(e) said data bus connecting each of said line adapters to said transceiver-controller means;

(f) multiplexor means including;

(f1) a plurality of groups of multiplexors whereby each group of multiplexors is connected to an associated line adapter for conveying bytes of data from said remote data set to said state machine processor means for subsequent transfer to said host computer, and wherein each said group of multiplexors includes;

(f1a) coded input signal means for identifying the particular timing and protocol discipline required for the said associated line adapter.

2. The network of claim 1, wherein each of said plurality of line adapter means includes:

(a) line adapter memory means for buffering data being transferred between said state machine processor means and said remote data set;

said line adapter memory means including a plurality of RAM storage means, each one of said RAM storage means being dedicated to a said plurality of line adapters.

3. The network of claim 1, wherein each one of said RAM storage means includes:

(a) memory space for receiving and storing said operational codes from said host computer.

4. The network of claim 1, wherein said state machine processor means includes:

(a) means to generate result/data for transmission to said host computer after execution of a said I/O data transfer command from said host computer.

5. An network for handling data transfer operations between a main host computer and a plurality of remote data sets, said network comprising:

(a) said main host computer being connected to a distribution control circuit means, and including;

(a1) first memory means for storing I/O data transfer commands for initiating data transfers to/from a plurality of remote data sets;

(a2) second memory means for storing operational codes for transmittal to each one of a plurality of line adapter memory means, said operational codes including control information on a variety of timing and protocol disciplines;

(a3) third memory means for storing data to be transmitted to/received from said remote data sets;

(a4) a main processor means for utilizing said first, second and third memory means for managing a plurality of line support processors;

(b) distribution control circuit means functioning to connect and disconnect said main host computer to/from a selected one of a plurality of line support processors;

(c) said line support processors operating to execute said I/O data transfer commands and for selecting the appropriate timing and protocol discipline for data transfers with each of said remote data sets, wherein each of said line support processors includes;

(c1) a data link interface circuit means connecting said distribution control circuit means to an internal processor means and to a line adapter means;

(c2) said internal processing means including an internal processor operating to translate said operational codes into control data for managing each selected line adapter to execute data transfers according to the appropriate timing and line discipline for the remote data set connected to the selected line adapter, said internal processing means including;

(c2a) auxiliary memory means for storing said operational codes;

(c2b) means for selecting a particular line adapter for data transfer operations and for identifying and enabling the said appropriate timing and protocol discipline to be used by said selected particular line adapter;

(d) said line adapter means including;

(d1) a plurality of line adapters, each of which provides a line connection to said remote data set and operates to execute data transfers between said line adapter means and said remote data set with the appropriately selected line discipline and protocol, under control of said internal processor means;

(d2) line adapter memory means for buffering data being transferred to/from said remote data set and to/from said main host computer;

(d3) switching means for connecting a selected line adapter to said internal processor or to an associated group of multiplexors in a multiplexor means;

(d4) said multiplexor means including;

(d4a) a plurality of groups of multiplexors wherein each group is connected to receive the outputs of an associated line adapter for transfer of data bytes to said line adapter memory means for subsequent handling by said internal processor;

(d4b) identification signal input means, for each group of multiplexors connected to an associated line adapter, for generating an identification signal to said internal processor means to enable said internal processor means to generate said appropriate control data for said selected line adapter;

(e) said plurality of remote data sets being connected so that each data set has its individual data communication line to an associated one of said line adapters.