Input circuit for infrared detector

• US 4,633,086 A
• Filed: 04/09/1985
• Issued: 12/30/1986
• Est. Priority Date: 04/09/1985
• Status: Expired due to Term

• Current Assignee: Grumman Aerospace Corporation (Northrop Grumman Corporation)
• Original Assignee: Grumman Aerospace Corporation (Northrop Grumman Corporation)
• Inventors: Parrish, William J.
• Primary Examiner(s): Howell, Janice A.
• Assistant Examiner(s): Hannaher, Constantine
• Application Number:
  US06/721,425
• Time in Patent Office: 630 Days
• Field of Search: 250/332, 250/338 SE, 250/338 R, 250/370 JX, 250/370 G, 250/370 R, 307/297, 357/32, 323/311, 323/312
• US Class Current: 250/338.1
• CPC Class Codes: H01L 27/14881 of the hybrid type

Abstract

A method and circuit are provided for interfacing an infrared detector to a common power supply and signal processing circuitry. A multichannel input circuit including a plurality of buffer circuits and a common bias network is formed on a single semiconductor substrate. The common bias network reduces the necessary connections between the substrate and the external power supply. The bias network is operative to reduce power level variations in the signal from the external power supply. Each channel includes a negative feedback circuit to maintain a dedicated detector in a zero bias condition, thus reducing 1/f noise and enhancing the signal-to-noise ratio of the circuit. The load to each channel is adjustable to maintain the detector in the zero bias condition.

Claims

1. An input circuit for a multichannel infrared detection system comprising a bias network connectable to the output of an external power supply, and a plurality of detector channels, each of said channels being connectable to a dedicated detector element and having at least one semiconductor device commonly connected to said bias network, said detector channels and said bias network being formed on a common semiconductor substrate, said bias network including circuitry to reduce power level variations present in the output from the external power supply and to thereby generate a low level bias signal, said bias signal being sufficient to bias at least one detector channel semiconductor device in each detector channel into a linear region of operation.

2. The circuit as recited in claim 1 wherein each of said detector channels is substantially identical.

3. The circuit as recited in claim 2 wherein each of said commonly connected detector channel semiconductor devices have substantially the same threshold level.

4. The circuit as recited in claim 1 wherein each of said detector channels receives substantially the same low level bias signal from said bias network.

5. The circuit as recited in claim 2 wherein said bias network comprises a feedback circuit disposed in parallel electrical relation to said detector channels, said feedback circuit being operative to facilitate said reduced power level variations and to reduce cross talk between detector channels.

6. The circuit as recited in claim 5 wherein said feedback circuit is substantially identical for each of said detector channels.

7. The system as recited in claim 5 wherein said bias network is operative to reduce power level variations to approximately one-tenth of the power level variations in the output from the external power supply.

8. The circuit as recited in claim 4 wherein the input circuit includes 64 detector channels.

9. The circuit as recited in claim 8 wherein said bias signal to each detector channel is approximately 40 nanoamps.

10. The circuit as recited in claim 1 wherein each of said detector channels comprises:

an input circuit;

a load circuit; and

a feedback circuit;

said input circuit comprising an input FET having a gate connectable to a first lead of a dedicated detector element, a source connected to said bias network and a drain connected to said load circuit;

said feedback circuit comprising a feedback FET having a gate connected to the drain of said input FET, a source connected to the gate of said input FET and a drain connectable to signal processing circuitry;

said load circuit comprising a load FET and adaptive biasing circuitry connected thereto, said load FET having a drain connected to said input FET drain and a source connected to a reference voltage, said adaptive biasing circuitry being operative to maintain said load FET in a conductive condition such that said load circuit functions as a constant current load to said input FET, said constant current load being at a load level corresponding to the output of said input FET when said reference voltage is applied to the gate of said input FET;

said feedback FET being operative to receive the output of said input FET in excess of said constant load level so as to regulate the conduction of said feedback FET to thereby maintain the gate of said input FET at approximately said reference voltage.

11. The circuit as recited in claim 10 wherein said input FET circuit further comprises a first switch connected to the gate of said input FET and to said reference voltage level, said first switch being operative to apply said reference voltage level to the gate of said input FET thereby short circuiting said detector.

12. The circuit as recited in claim 10 wherein said adaptive biasing circuitry comprises:

a capacitor having first lead connected to the gate of said load FET and a second lead connected to the source of said load FET; and

a second switch connected to the drain and to the gate of said load FET, said second switch being adapted to be temporarily closed, upon the closure of said first switch, to apply a first voltage to the gate of said load FET, said first voltage being maintained on the gate of said load FET by said capacitor when said second switch is opened.

13. The circuit as recited in claim 10 further comprising a HgCdTe detector element connected to each of said detector channels.

14. A method of generating signal levels for providing low level biasing for a multichannel infrared detection circuit, the method comprising the steps of:

receiving a signal from an external power source at the input of a common bias network for a multichannel infrared detection circuit, said bias network and each channel of said multichannel detector circuit being formed on a common semiconductor substrate;

commonly connecting each channel of said multichannel bias circuit to an output of said bias network, said common connections being effective to collectively load said bias network into a linear operational condition;

reducing power level variations in said received signal to form a low level bias signal for communication to each of said channels; and

communicating said low level bias signal to each of said detector channels, said bias signal being sufficient to bias each of said channels into a linear operational region.

15. The method as recited in claim 14 further including the steps of reducing the impedance at said common connection to said bias network and preventing cross talk between channels of said multichannel detector circuit.

16. The method as recited in claim 14 further including the steps of:

connecting a first lead of an infrared detector to the input of a dedicated channel of said multichannel detector circuit, each channel comprising an input circuit, a load circuit and a feedback circuit;

connecting a second lead of said detector to a reference voltage;

temporarily shorting at least a portion of the input and load circuits to adaptively set said channel for stable operation when the input to said channel is at said reference voltage, thereby causing the voltage across said detector to be zero volts;

generating an output from said detector in response to infrared irradiation of said detector; and

generating a variable feedback signal in response to the output of said detector, said feedback signal being effective to maintain the input to said channel at approximately said reference voltage.

17. The method as recited in claim 16 wherein said step of temporarily shorting at least a portion of the input and load circuits to adaptively set said channel for stable operation comprises the steps of:

shorting said first and second leads of said detector; and

biasing said load circuit to operate as a constant current load to said input circuit, said constant current load level corresponding to the output of said input circuit upon the application of said reference voltage to said input circuit.

18. The method as recited in claim 16, wherein the step of generating a variable feedback signal comprises the step of:

applying the output from said input circuit, in excess of said constant current load level, to said feedback circuit so as to cause said feedback circuit to maintain the channel input at said reference voltage.

19. A method of generating a signal in response to irradiation of an infrared detector comprising the steps of:

receiving a signal from external power supply at the input of a common bias network of a multichannel infrared detection circuit, said bias network and each channel of said multichannel detector circuit being formed on a common semiconductor substrate, each of said channels comprising an input FET, a load FET and a feedback FET;

connecting a first lead of a dedicated infrared detector to the gate of said input FET, said input FET having a source connected to a common output of said bias network and a drain connected to both the source of said load FET and to the gate of said feedback FET, said input FET in each of said channels receiving approximately the same bias signal from said bias network, said bias signal being sufficient to bias said input FET in each of said channels into a linear operational condition;

connecting a second lead of said detector to a reference voltage;

connecting the source of said feedback FET to the gate of said input FET;

connecting a storage device between the gate and source of said load FET;

temporarily shorting the gate of said input FET to said reference voltage so as to provide zero volts across said detector;

temporarily shorting the gate and drain of said load FET;

disconnecting the gate of said input FET from said reference voltage;

disconnecting the short between the gate and drain of said load FET so as to bias said load FET to operate as a constant current load to said input FET, the level of said constant current load being equal to the current through said input FET when the base of said input FET is at said reference voltage;

irradiating said detector with infrared frequency energy;

feeding back to the gate of said feedback FET the portion of the current through said input FET in excess of said constant curent load level; and

generating an output from said feedback FET in response to said fedback current.